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https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [pipefetch.v] - Diff between revs 21 and 113
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| Rev 21 |
Rev 113 |
| Line 255... |
Line 255... |
cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
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cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
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<= i_wb_data;
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<= i_wb_data;
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initial r_addr_set = 1'b0;
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initial r_addr_set = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_new_pc))
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r_addr_set <= 1'b0;
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else if (i_new_pc)
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r_addr_set <= 1'b1;
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r_addr_set <= 1'b1;
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else if (i_clear_cache)
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r_addr_set <= 1'b0;
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// Now, read from the cache
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// Now, read from the cache
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wire w_cv; // Cache valid, address is in the cache
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wire w_cv; // Cache valid, address is in the cache
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reg r_cv;
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reg r_cv;
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assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
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assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
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| Line 291... |
Line 291... |
initial ill_address = 0;
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initial ill_address = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_err))
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if ((o_wb_cyc)&&(i_wb_err))
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ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
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ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
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assign o_illegal = (o_pc == ill_address);
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assign o_illegal = (o_pc == ill_address)&&(~i_rst)&&(~i_new_pc)&&(~i_clear_cache);
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endmodule
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endmodule
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