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Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [pipefetch.v] - Diff between revs 21 and 113

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Rev 21 Rev 113
Line 255... Line 255...
                        cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
                        cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
                                        <= i_wb_data;
                                        <= i_wb_data;
 
 
        initial r_addr_set = 1'b0;
        initial r_addr_set = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                if ((i_rst)||(i_new_pc))
                        r_addr_set <= 1'b0;
 
                else if (i_new_pc)
 
                        r_addr_set <= 1'b1;
                        r_addr_set <= 1'b1;
 
                else if (i_clear_cache)
 
                        r_addr_set <= 1'b0;
 
 
        // Now, read from the cache
        // Now, read from the cache
        wire    w_cv;   // Cache valid, address is in the cache
        wire    w_cv;   // Cache valid, address is in the cache
        reg     r_cv;
        reg     r_cv;
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
Line 291... Line 291...
        initial ill_address = 0;
        initial ill_address = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_err))
                if ((o_wb_cyc)&&(i_wb_err))
                        ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
                        ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
 
 
        assign  o_illegal = (o_pc == ill_address);
        assign  o_illegal = (o_pc == ill_address)&&(~i_rst)&&(~i_new_pc)&&(~i_clear_cache);
 
 
 
 
endmodule
endmodule
 
 
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