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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [pipemem.v] - Diff between revs 52 and 66

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Rev 52 Rev 66
Line 158... Line 158...
        assign  o_busy = cyc;
        assign  o_busy = cyc;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wreg <= fifo_oreg[rdaddr];
                o_wreg <= fifo_oreg[rdaddr];
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_wb_ack)
                // if (i_wb_ack) isn't necessary, since o_valid won't be true
 
                // then either.
                        o_result <= i_wb_data;
                        o_result <= i_wb_data;
 
 
        assign  o_pipe_stalled = (cyc)
        assign  o_pipe_stalled = (cyc)
                        &&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
                        &&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
 
 

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