URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [wbdmac.v] - Diff between revs 117 and 118

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Rev 117	Rev 118
Line 166...	Line 166...
`wire [(AW-1):0] bus_nracks;`	`wire [(AW-1):0] bus_nracks;`
`assign bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks };`	`assign bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks };`

`reg last_read_request, last_read_ack,`	`reg last_read_request, last_read_ack,`
`last_write_request, last_write_ack;`	`last_write_request, last_write_ack;`
`reg trigger, abort;`	`reg trigger, abort, user_halt;`

initial dma_state = `DMA_IDLE;	initial dma_state = `DMA_IDLE;
`initial o_interrupt = 1'b0;`	`initial o_interrupt = 1'b0;`
`initial cfg_len = {(AW){1'b0}};`	`initial cfg_len = {(AW){1'b0}};`
`initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};`	`initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};`
Line 191...	Line 191...
`// and thus to start.`	`// and thus to start.`
`if ((i_swb_stb)&&(i_swb_we))`	`if ((i_swb_stb)&&(i_swb_we))`
`begin`	`begin`
`case(i_swb_addr)`	`case(i_swb_addr)`
`2'b00: begin`	`2'b00: begin`
`if ((i_swb_data[27:16] == 12'hfed)`	`if ((i_swb_data[31:16] == 16'h0fed)`
`&&(cfg_len_nonzero))`	`&&(cfg_len_nonzero))`
dma_state <= `DMA_WAIT;	dma_state <= `DMA_WAIT;
`cfg_blocklen_sub_one`	`cfg_blocklen_sub_one`
`<= i_swb_data[(LGMEMLEN-1):0]`	`<= i_swb_data[(LGMEMLEN-1):0]`
`+ {(LGMEMLEN){1'b1}};`	`+ {(LGMEMLEN){1'b1}};`
Line 219...	Line 219...
`nwacks <= 0;`	`nwacks <= 0;`
`nwritten <= 0;`	`nwritten <= 0;`
`nread <= 0;`	`nread <= 0;`
`if (abort)`	`if (abort)`
dma_state <= `DMA_IDLE;	dma_state <= `DMA_IDLE;
	`else if (user_halt)`
	dma_state <= `DMA_IDLE;
`else if (trigger)`	`else if (trigger)`
dma_state <= `DMA_READ_REQ;	dma_state <= `DMA_READ_REQ;
`end`	`end`
`DMA_READ_REQ: begin	`DMA_READ_REQ: begin
`nwritten <= 0;`	`nwritten <= 0;`
Line 238...	Line 240...
`if (cfg_incs)`	`if (cfg_incs)`
`o_mwb_addr <= o_mwb_addr`	`o_mwb_addr <= o_mwb_addr`
`+ {{(AW-1){1'b0}},1'b1};`	`+ {{(AW-1){1'b0}},1'b1};`
`end`	`end`

	`if (user_halt)`
	dma_state <= `DMA_READ_ACK;
`if (i_mwb_err)`	`if (i_mwb_err)`
`begin`	`begin`
`cfg_len <= 0;`	`cfg_len <= 0;`
dma_state <= `DMA_IDLE;	dma_state <= `DMA_IDLE;
`end`	`end`

`if (abort)`	`if (abort)`
dma_state <= `DMA_IDLE;	dma_state <= `DMA_IDLE;
`if (i_mwb_ack)`	`if (i_mwb_ack)`
`begin`	`begin`
`nread <= nread+1;`	`nread <= nread+1;`
Line 264...	Line 269...
`end else if (i_mwb_ack)`	`end else if (i_mwb_ack)`
`begin`	`begin`
`nread <= nread+1;`	`nread <= nread+1;`
`if (last_read_ack) // (nread+1 == nracks)`	`if (last_read_ack) // (nread+1 == nracks)`
dma_state <= `DMA_PRE_WRITE;	dma_state <= `DMA_PRE_WRITE;
	`if (user_halt)`
	dma_state <= `DMA_IDLE;
`if (cfg_incs)`	`if (cfg_incs)`
`cfg_raddr <= cfg_raddr`	`cfg_raddr <= cfg_raddr`
`+ {{(AW-1){1'b0}},1'b1};`	`+ {{(AW-1){1'b0}},1'b1};`
`end`	`end`
`if (abort)`	`if (abort)`
Line 301...	Line 308...
`if (i_mwb_ack)`	`if (i_mwb_ack)`
`begin`	`begin`
`nwacks <= nwacks+1;`	`nwacks <= nwacks+1;`
`cfg_len <= cfg_len +{(AW){1'b1}}; // -1`	`cfg_len <= cfg_len +{(AW){1'b1}}; // -1`
`end`	`end`
	`if (user_halt)`
	dma_state <= `DMA_WRITE_ACK;
`if (abort)`	`if (abort)`
dma_state <= `DMA_IDLE;	dma_state <= `DMA_IDLE;
`end`	`end`
`DMA_WRITE_ACK: begin	`DMA_WRITE_ACK: begin
`if (i_mwb_err)`	`if (i_mwb_err)`
Line 464...	Line 473...
`always @(posedge i_clk)`	`always @(posedge i_clk)`
`abort <= (i_rst)\|\|((i_swb_stb)&&(i_swb_we)`	`abort <= (i_rst)\|\|((i_swb_stb)&&(i_swb_we)`
`&&(i_swb_addr == 2'b00)`	`&&(i_swb_addr == 2'b00)`
`&&(i_swb_data == 32'hffed0000));`	`&&(i_swb_data == 32'hffed0000));`

	`initial user_halt = 1'b0;`
	`always @(posedge i_clk)`
	user_halt <= ((user_halt)&&(dma_state != `DMA_IDLE))
	\|\|((i_swb_stb)&&(i_swb_we)&&(dma_state != `DMA_IDLE)
	`&&(i_swb_addr == 2'b00)`
	`&&(i_swb_data == 32'hafed0000));`

`endmodule`	`endmodule`


`No newline at end of file`	`No newline at end of file`

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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [wbdmac.v] - Diff between revs 117 and 118