| Line 43... |
Line 43... |
o_ext_int,
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o_ext_int,
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// Wishbone slave interface for debugging purposes
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// Wishbone slave interface for debugging purposes
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data
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o_dbg_ack, o_dbg_stall, o_dbg_data
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_zip_debug
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, o_cpu_debug
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`endif
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`endif
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);
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);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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LGICACHE=6, START_HALTED=0,
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LGICACHE=6, START_HALTED=0,
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AW=ADDRESS_WIDTH;
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AW=ADDRESS_WIDTH;
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| Line 69... |
Line 69... |
output reg o_dbg_ack;
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output reg o_dbg_ack;
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output wire o_dbg_stall;
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output wire o_dbg_stall;
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output wire [31:0] o_dbg_data;
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output wire [31:0] o_dbg_data;
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//
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//
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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output wire [31:0] o_zip_debug;
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output wire [31:0] o_cpu_debug;
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`endif
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`endif
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|
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//
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//
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//
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//
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//
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//
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| Line 117... |
Line 117... |
else if ((cmd_step)||(cpu_break))
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else if ((cmd_step)||(cpu_break))
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cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
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|
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initial cmd_clear_pf_cache = 1'b0;
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initial cmd_clear_pf_cache = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
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cmd_clear_pf_cache <= 1'b0;
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&&((i_dbg_data[11])||(i_dbg_data[6]));
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else if (dbg_cmd_write)
|
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cmd_clear_pf_cache <= i_dbg_data[11];
|
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else
|
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cmd_clear_pf_cache <= 1'b0;
|
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//
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//
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initial cmd_step = 1'b0;
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initial cmd_step = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]);
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cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]);
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//
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//
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| Line 174... |
Line 170... |
cpu_dbg_cc, cpu_break,
|
cpu_dbg_cc, cpu_break,
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o_wb_cyc, o_wb_stb,
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o_wb_cyc, o_wb_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)),
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(i_wb_err)||(cpu_lcl_cyc),
|
cpu_op_stall, cpu_pf_stall, cpu_i_count
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cpu_op_stall, cpu_pf_stall, cpu_i_count
|
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
, o_zip_debug
|
, o_cpu_debug
|
`endif
|
`endif
|
);
|
);
|
|
|
// Return debug response values
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// Return debug response values
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assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
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assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
|
initial o_dbg_ack = 1'b0;
|
initial o_dbg_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
|
o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
|
assign o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
|
assign o_dbg_stall= 1'b0; //(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
|
|
|
assign o_ext_int = (cmd_halt) && (~i_wb_stall);
|
assign o_ext_int = (cmd_halt) && (~i_wb_stall);
|
|
|
endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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