| Line 1741... |
Line 1741... |
`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_debug <= {
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o_debug <= {
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/*
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/*
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o_break, i_wb_err, pf_pc[1:0],
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o_break, i_wb_err, pf_pc[1:0],
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//
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flags,
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flags,
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//
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pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
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pf_valid, dcdvalid, opvalid, alu_valid,
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//
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mem_valid,
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op_ce, alu_ce, mem_ce,
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op_ce, alu_ce, mem_ce,
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//
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//
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master_ce,
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master_ce, opvalid_alu, opvalid_mem,
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opvalid_alu, opvalid_mem, alu_stall,
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//
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//
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mem_busy, op_pipe,
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alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
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`ifdef OPT_PIPELINED_BUS_ACCESS
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mem_pipe_stalled,
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`else
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1'b0,
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`endif
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mem_we,
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mem_we,
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//
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// ((opvalid_alu)&&(alu_stall))
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// ((opvalid_alu)&&(alu_stall))
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// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
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// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
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// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
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// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
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// opA[23:20], opA[3:0],
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// opA[23:20], opA[3:0],
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gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
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gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
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*/
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*/
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o_break, i_wb_err, o_wb_gbl_cyc, o_wb_gbl_stb,
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pf_valid, dcdvalid, opvalid, alu_valid,
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mem_valid, dcd_ce, op_ce, alu_ce,
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mem_ce,
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//
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(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
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gie, sleep,
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{ ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(o_wb_we))
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? o_wb_data[15:0]
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: ((o_wb_gbl_cyc)&&(~o_wb_we)&&(i_wb_ack))
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? i_wb_data[15:0]
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: o_wb_addr[15:0]
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}
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/*
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/*
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i_rst, master_ce, (new_pc),
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i_rst, master_ce, (new_pc),
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((dcd_early_branch)&&(dcdvalid)),
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((dcd_early_branch)&&(dcdvalid)),
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pf_valid, pf_illegal,
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pf_valid, pf_illegal,
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op_ce, dcd_ce, dcdvalid, dcd_stalled,
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op_ce, dcd_ce, dcdvalid, dcd_stalled,
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pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
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pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
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pf_pc[7:0], pf_addr[7:0]
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pf_pc[7:0], pf_addr[7:0]
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*/
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*/
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/*
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i_wb_err, gie, alu_illegal,
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i_wb_err, gie, alu_illegal,
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(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
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(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
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mem_busy,
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mem_busy,
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(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
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(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
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o_wb_addr[8:0] }
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o_wb_addr[8:0] }
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: { instruction[31:21] },
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: { instruction[31:21] },
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pf_valid, (pf_valid) ? alu_pc[14:0]
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pf_valid, (pf_valid) ? alu_pc[14:0]
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:{ pf_cyc, pf_stb, pf_pc[12:0] }
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:{ pf_cyc, pf_stb, pf_pc[12:0] }
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*/
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/*
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/*
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i_wb_err, gie, new_pc, dcd_early_branch, // 4
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i_wb_err, gie, new_pc, dcd_early_branch, // 4
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pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
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pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
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instruction[30:27], // 4
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instruction[30:27], // 4
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dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
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dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
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