| Line 1043... |
Line 1043... |
if (i_rst)
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if (i_rst)
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begin
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begin
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alu_wr <= 1'b0;
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alu_wr <= 1'b0;
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alF_wr <= 1'b0;
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alF_wr <= 1'b0;
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end else if (alu_ce)
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end else if (alu_ce)
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`ifdef OPT_ILLEGAL_INSTRUCTION
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begin
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|
// alu_reg <= opR;
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|
alu_wr <= (opR_wr)&&(set_cond)&&(~op_illegal);
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alF_wr <= (opF_wr)&&(set_cond);
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|
end else if (~alu_busy) begin
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// These are strobe signals, so clear them if not
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|
// set for any particular clock
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alu_wr <= (i_halt)&&(i_dbg_we);
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alF_wr <= 1'b0;
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end
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`else
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begin
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begin
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// alu_reg <= opR;
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// alu_reg <= opR;
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alu_wr <= (opR_wr)&&(set_cond);
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alu_wr <= (opR_wr)&&(set_cond);
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alF_wr <= (opF_wr)&&(set_cond);
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alF_wr <= (opF_wr)&&(set_cond);
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end else if (~alu_busy) begin
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end else if (~alu_busy) begin
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// These are strobe signals, so clear them if not
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// These are strobe signals, so clear them if not
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// set for any particular clock
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// set for any particular clock
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alu_wr <= (i_halt)&&(i_dbg_we);
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alu_wr <= (i_halt)&&(i_dbg_we);
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alF_wr <= 1'b0;
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alF_wr <= 1'b0;
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end
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end
|
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`endif
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|
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`ifdef OPT_VLIW
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`ifdef OPT_VLIW
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reg r_alu_phase;
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reg r_alu_phase;
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initial r_alu_phase = 1'b0;
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initial r_alu_phase = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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| Line 1089... |
Line 1102... |
if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
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&&(~mem_stalled)))
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&&(~mem_stalled)))
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alu_pc <= op_pc;
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alu_pc <= op_pc;
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|
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`ifdef OPT_ILLEGAL_INSTRUCTION
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`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg r_alu_illegal;
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/*
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initial r_alu_illegal = 0;
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reg r_alu_illegal;
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always @(posedge i_clk)
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initial r_alu_illegal = 0;
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if (clear_pipeline)
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always @(posedge i_clk)
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r_alu_illegal <= 1'b0;
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if (clear_pipeline)
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else if ((alu_ce)||(mem_ce))
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r_alu_illegal <= 1'b0;
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r_alu_illegal <= op_illegal;
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else if ((alu_ce)||(mem_ce))
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assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
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r_alu_illegal <= op_illegal;
|
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||(r_alu_illegal);
|
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*/
|
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assign alu_illegal = (alu_illegal_op);
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`endif
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`endif
|
|
|
// This _almost_ is equal to (alu_ce)||(mem_ce). The only
|
// This _almost_ is equal to (alu_ce)||(mem_ce). The only
|
// problem is that mem_ce is gated by the set_cond, and
|
// problem is that mem_ce is gated by the set_cond, and
|
// the PC will be valid independent of the set condition. Hence, this
|
// the PC will be valid independent of the set condition. Hence, this
|
| Line 1185... |
Line 1201... |
// Note that the flags needed to be checked before issuing the
|
// Note that the flags needed to be checked before issuing the
|
// bus instruction, so they don't need to be checked here.
|
// bus instruction, so they don't need to be checked here.
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// check for that here either.
|
// check for that here either.
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign wr_reg_ce = (~alu_illegal)&&
|
assign wr_reg_ce = (((alu_wr)&&(~clear_pipeline)
|
(((alu_wr)&&(~clear_pipeline)
|
|
&&((alu_valid)||(div_valid)||(fpu_valid)))
|
&&((alu_valid)||(div_valid)||(fpu_valid)))
|
||(mem_valid));
|
||(mem_valid));
|
`else
|
`else
|
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
|
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
|
`endif
|
`endif
|
