| Line 1043... |
Line 1043... |
if (i_rst)
|
if (i_rst)
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begin
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begin
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alu_wr <= 1'b0;
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alu_wr <= 1'b0;
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alF_wr <= 1'b0;
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alF_wr <= 1'b0;
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end else if (alu_ce)
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end else if (alu_ce)
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`ifdef OPT_ILLEGAL_INSTRUCTION
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begin
|
|
// alu_reg <= opR;
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|
alu_wr <= (opR_wr)&&(set_cond)&&(~op_illegal);
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alF_wr <= (opF_wr)&&(set_cond);
|
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end else if (~alu_busy) begin
|
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// These are strobe signals, so clear them if not
|
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// set for any particular clock
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alu_wr <= (i_halt)&&(i_dbg_we);
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alF_wr <= 1'b0;
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end
|
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`else
|
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begin
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begin
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// alu_reg <= opR;
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// alu_reg <= opR;
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alu_wr <= (opR_wr)&&(set_cond);
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alu_wr <= (opR_wr)&&(set_cond);
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alF_wr <= (opF_wr)&&(set_cond);
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alF_wr <= (opF_wr)&&(set_cond);
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end else if (~alu_busy) begin
|
end else if (~alu_busy) begin
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// These are strobe signals, so clear them if not
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// These are strobe signals, so clear them if not
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// set for any particular clock
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// set for any particular clock
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alu_wr <= (i_halt)&&(i_dbg_we);
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alu_wr <= (i_halt)&&(i_dbg_we);
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alF_wr <= 1'b0;
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alF_wr <= 1'b0;
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end
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end
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`endif
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|
|
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`ifdef OPT_VLIW
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`ifdef OPT_VLIW
|
reg r_alu_phase;
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reg r_alu_phase;
|
initial r_alu_phase = 1'b0;
|
initial r_alu_phase = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 1102... |
Line 1089... |
if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
&&(~mem_stalled)))
|
&&(~mem_stalled)))
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alu_pc <= op_pc;
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alu_pc <= op_pc;
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
/*
|
reg r_alu_illegal;
|
reg r_alu_illegal;
|
initial r_alu_illegal = 0;
|
initial r_alu_illegal = 0;
|
always @(posedge i_clk)
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always @(posedge i_clk)
|
if (clear_pipeline)
|
if (clear_pipeline)
|
r_alu_illegal <= 1'b0;
|
r_alu_illegal <= 1'b0;
|
else if ((alu_ce)||(mem_ce))
|
else if ((alu_ce)||(mem_ce))
|
r_alu_illegal <= op_illegal;
|
r_alu_illegal <= op_illegal;
|
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
|
||(r_alu_illegal);
|
|
*/
|
|
assign alu_illegal = (alu_illegal_op);
|
|
`endif
|
`endif
|
|
|
// This _almost_ is equal to (alu_ce)||(mem_ce). The only
|
// This _almost_ is equal to (alu_ce)||(mem_ce). The only
|
// problem is that mem_ce is gated by the set_cond, and
|
// problem is that mem_ce is gated by the set_cond, and
|
// the PC will be valid independent of the set condition. Hence, this
|
// the PC will be valid independent of the set condition. Hence, this
|
| Line 1201... |
Line 1185... |
// Note that the flags needed to be checked before issuing the
|
// Note that the flags needed to be checked before issuing the
|
// bus instruction, so they don't need to be checked here.
|
// bus instruction, so they don't need to be checked here.
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// check for that here either.
|
// check for that here either.
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign wr_reg_ce = (((alu_wr)&&(~clear_pipeline)
|
assign wr_reg_ce = (~alu_illegal)&&
|
|
(((alu_wr)&&(~clear_pipeline)
|
&&((alu_valid)||(div_valid)||(fpu_valid)))
|
&&((alu_valid)||(div_valid)||(fpu_valid)))
|
||(mem_valid));
|
||(mem_valid));
|
`else
|
`else
|
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
|
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
|
`endif
|
`endif
|
| Line 1292... |
Line 1277... |
||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
|
||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
|
`else
|
`else
|
assign o_break = (((break_en)||(~op_gie))&&(op_break)
|
assign o_break = (((break_en)||(~op_gie))&&(op_break)
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
&&(~clear_pipeline))
|
&&(~clear_pipeline))
|
||((~alu_gie)&&(bus_err));
|
||((~alu_gie)&&(bus_err))
|
|
||((~alu_gie)&&(div_valid)&&(div_error))
|
|
||((~alu_gie)&&(fpu_valid)&&(fpu_error));
|
`endif
|
`endif
|
|
|
|
|
// The sleep register. Setting the sleep register causes the CPU to
|
// The sleep register. Setting the sleep register causes the CPU to
|
// sleep until the next interrupt. Setting the sleep register within
|
// sleep until the next interrupt. Setting the sleep register within
|
| Line 1645... |
Line 1632... |
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
|
|
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_debug <= {
|
o_debug <= {
|
pf_pc[3:0], flags,
|
i_wb_err, pf_pc[2:0], flags,
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
op_ce, alu_ce, mem_ce,
|
op_ce, alu_ce, mem_ce,
|
//
|
//
|
master_ce, opvalid_alu, opvalid_mem,
|
master_ce, opvalid_alu, opvalid_mem,
|
//
|
//
|
