| Line 135... |
Line 135... |
`endif
|
`endif
|
);
|
);
|
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
|
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
|
LGICACHE=6;
|
LGICACHE=6;
|
`ifdef OPT_MULTIPLY
|
`ifdef OPT_MULTIPLY
|
parameter IMPLEMENT_MPY = 1;
|
parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
|
`else
|
`else
|
parameter IMPLEMENT_MPY = 0;
|
parameter IMPLEMENT_MPY = 0;
|
`endif
|
`endif
|
`ifdef OPT_DIVIDE
|
`ifdef OPT_DIVIDE
|
parameter IMPLEMENT_DIVIDE = 1;
|
parameter IMPLEMENT_DIVIDE = 1;
|
| Line 867... |
Line 867... |
|
|
initial r_op_lock = 1'b0;
|
initial r_op_lock = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_op_lock <= 1'b0;
|
r_op_lock <= 1'b0;
|
else if ((op_ce)&&(dcd_lock))
|
else if (op_ce)
|
r_op_lock <= 1'b1;
|
r_op_lock <= (dcd_lock)&&(~clear_pipeline);
|
else if ((op_ce)||(clear_pipeline))
|
|
r_op_lock <= 1'b0;
|
|
assign op_lock = r_op_lock;
|
assign op_lock = r_op_lock;
|
|
|
end else begin
|
end else begin
|
assign op_lock_stall = 1'b0;
|
assign op_lock_stall = 1'b0;
|
assign op_lock = 1'b0;
|
assign op_lock = 1'b0;
|
| Line 1178... |
Line 1176... |
wire bus_lock;
|
wire bus_lock;
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
generate
|
generate
|
if (IMPLEMENT_LOCK != 0)
|
if (IMPLEMENT_LOCK != 0)
|
begin
|
begin
|
reg r_bus_lock;
|
reg [1:0] r_bus_lock;
|
initial r_bus_lock = 1'b0;
|
initial r_bus_lock = 2'b00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_bus_lock <= 1'b0;
|
r_bus_lock <= 2'b00;
|
else if ((op_ce)&&(op_lock))
|
else if ((op_ce)&&(op_lock))
|
r_bus_lock <= 1'b1;
|
r_bus_lock <= 2'b11;
|
else if (~opvalid_mem)
|
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
|
r_bus_lock <= 1'b0;
|
r_bus_lock <= r_bus_lock + 2'b11;
|
assign bus_lock = r_bus_lock;
|
assign bus_lock = |r_bus_lock;
|
end else begin
|
end else begin
|
assign bus_lock = 1'b0;
|
assign bus_lock = 1'b0;
|
end endgenerate
|
end endgenerate
|
`else
|
`else
|
assign bus_lock = 1'b0;
|
assign bus_lock = 1'b0;
|
| Line 1447... |
Line 1445... |
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
initial ill_err_i = 1'b0;
|
initial ill_err_i = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ill_err_i <= 1'b0;
|
ill_err_i <= 1'b0;
|
// The debug interface can clear this bit
|
// Only the debug interface can clear this bit
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
&&(~wr_reg_vl[`CPU_ILL_BIT]))
|
&&(~wr_reg_vl[`CPU_ILL_BIT]))
|
ill_err_i <= 1'b0;
|
ill_err_i <= 1'b0;
|
else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
|
else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
|
ill_err_i <= 1'b1;
|
ill_err_i <= 1'b1;
|
| Line 1707... |
Line 1705... |
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
|
|
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_debug <= {
|
o_debug <= {
|
/*
|
o_break, i_wb_err, pf_pc[1:0],
|
i_wb_err, pf_pc[2:0],
|
flags,
|
flags,
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
op_ce, alu_ce, mem_ce,
|
op_ce, alu_ce, mem_ce,
|
//
|
//
|
master_ce, opvalid_alu, opvalid_mem,
|
master_ce, opvalid_alu, opvalid_mem,
|
//
|
//
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
mem_we,
|
mem_we,
|
// ((opvalid_alu)&&(alu_stall))
|
// ((opvalid_alu)&&(alu_stall))
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
// opA[23:20], opA[3:0],
|
// opA[23:20], opA[3:0],
|
gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
|
gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
|
|
*/
|
|
/*
|
/*
|
i_rst, master_ce, (new_pc),
|
i_rst, master_ce, (new_pc),
|
((dcd_early_branch)&&(dcdvalid)),
|
((dcd_early_branch)&&(dcdvalid)),
|
pf_valid, pf_illegal,
|
pf_valid, pf_illegal,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
| Line 1741... |
Line 1737... |
o_wb_addr[8:0] }
|
o_wb_addr[8:0] }
|
: { instruction[31:21] },
|
: { instruction[31:21] },
|
pf_valid, (pf_valid) ? alu_pc[14:0]
|
pf_valid, (pf_valid) ? alu_pc[14:0]
|
:{ pf_cyc, pf_stb, pf_pc[12:0] }
|
:{ pf_cyc, pf_stb, pf_pc[12:0] }
|
*/
|
*/
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
/*
|
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
instruction[30:27], // 4
|
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
|
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
|
instruction[30:27], // 4
|
dcdvalid,
|
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
|
((dcd_early_branch)&&(~clear_pipeline)) // 15
|
dcdvalid,
|
? dcd_branch_pc[14:0]:pf_pc[14:0]
|
((dcd_early_branch)&&(~clear_pipeline)) // 15
|
|
? dcd_branch_pc[14:0]:pf_pc[14:0]
|
|
*/
|
};
|
};
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
