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Line 69... |
// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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| Line 290... |
Line 290... |
reg opA_alu, opA_mem;
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reg opA_alu, opA_mem;
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reg opB_alu, opB_mem;
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reg opB_alu, opB_mem;
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`endif
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`endif
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`ifdef OPT_ILLEGAL_INSTRUCTION
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`ifdef OPT_ILLEGAL_INSTRUCTION
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reg op_illegal;
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reg op_illegal;
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`else
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wire op_illegal;
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assign op_illegal = 1'b0;
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`endif
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`endif
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reg op_break;
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reg op_break;
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wire op_lock;
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wire op_lock;
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Line 348... |
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
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assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
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&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
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&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
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&&(set_cond);
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&&(set_cond);
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// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
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// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
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wire adf_ce;
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wire adf_ce, adf_ce_unconditional;
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assign adf_ce = (master_ce)&&(~clear_pipeline)&&(opvalid)
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assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid)
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&&(~opvalid_mem)&&(~mem_rdbusy)&&(~div_busy)
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&&(~opvalid_mem)&&(~mem_rdbusy)&&(~div_busy)
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&&(~fpu_busy)&&(set_cond);
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&&(~fpu_busy);
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assign adf_ce = (adf_ce_unconditional)&&(set_cond);
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//
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//
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//
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//
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// PIPELINE STAGE #5 :: Write-back
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// PIPELINE STAGE #5 :: Write-back
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// Variable declarations
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// Variable declarations
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//
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//
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| Line 459... |
Line 464... |
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
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||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
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&&(wr_write_cc)) // Case 3
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&&(wr_write_cc)) // Case 3
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||((opvalid)&&(op_lock)&&(op_lock_stall))
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||((opvalid)&&(op_lock)&&(op_lock_stall))
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||((opvalid)&&(op_break))
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||((opvalid)&&(op_break))
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||(div_busy)||(fpu_busy);
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||(div_busy)||(fpu_busy);
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assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))
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assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
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&&(~alu_stall)
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&&(~clear_pipeline);
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&&(~clear_pipeline);
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`else
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`else
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assign alu_stall = ((~master_ce)&&(opvalid_alu))
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assign alu_stall = ((~master_ce)&&(opvalid_alu))
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||((opvalid_alu)&&(op_break));
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||((opvalid_alu)&&(op_break));
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assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
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assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
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Line 845... |
opvalid_alu <= (dcdALU)&&(w_opvalid);
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opvalid_alu <= (dcdALU)&&(w_opvalid);
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opvalid_mem <= (dcdM)&&(w_opvalid);
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opvalid_mem <= (dcdM)&&(w_opvalid);
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opvalid_div <= (dcdDV)&&(w_opvalid);
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opvalid_div <= (dcdDV)&&(w_opvalid);
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opvalid_fpu <= (dcdFP)&&(w_opvalid);
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opvalid_fpu <= (dcdFP)&&(w_opvalid);
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`endif
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`endif
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end else if ((clear_pipeline)||(adf_ce)||(mem_ce))
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end else if ((clear_pipeline)||(adf_ce_unconditional)||(mem_ce))
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begin
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begin
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opvalid <= 1'b0;
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opvalid <= 1'b0;
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opvalid_alu <= 1'b0;
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opvalid_alu <= 1'b0;
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opvalid_mem <= 1'b0;
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opvalid_mem <= 1'b0;
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opvalid_div <= 1'b0;
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opvalid_div <= 1'b0;
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| Line 1131... |
Line 1135... |
reg r_alu_phase;
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reg r_alu_phase;
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initial r_alu_phase = 1'b0;
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initial r_alu_phase = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_alu_phase <= 1'b0;
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r_alu_phase <= 1'b0;
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else if ((adf_ce)||(mem_ce))
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else if ((adf_ce_unconditional)||(mem_ce))
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r_alu_phase <= op_phase;
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r_alu_phase <= op_phase;
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assign alu_phase = r_alu_phase;
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assign alu_phase = r_alu_phase;
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`else
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`else
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assign alu_phase = 1'b0;
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assign alu_phase = 1'b0;
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`endif
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`endif
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (adf_ce)
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if (adf_ce_unconditional)
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alu_reg <= opR;
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alu_reg <= opR;
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else if ((i_halt)&&(i_dbg_we))
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else if ((i_halt)&&(i_dbg_we))
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alu_reg <= i_dbg_reg;
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alu_reg <= i_dbg_reg;
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//
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//
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| Line 1155... |
Line 1159... |
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
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dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
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reg [31:0] dbg_val;
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reg [31:0] dbg_val;
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always @(posedge i_clk)
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always @(posedge i_clk)
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dbg_val <= i_dbg_data;
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dbg_val <= i_dbg_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((adf_ce)||(mem_ce))
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if ((adf_ce_unconditional)||(mem_ce))
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alu_gie <= op_gie;
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alu_gie <= op_gie;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((adf_ce)
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if ((adf_ce_unconditional)
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||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
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||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
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&&(~mem_stalled)))
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&&(~mem_stalled)))
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alu_pc <= op_pc;
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alu_pc <= op_pc;
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`ifdef OPT_ILLEGAL_INSTRUCTION
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`ifdef OPT_ILLEGAL_INSTRUCTION
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| Line 1179... |
Line 1183... |
initial r_alu_pc_valid = 1'b0;
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initial r_alu_pc_valid = 1'b0;
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initial mem_pc_valid = 1'b0;
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initial mem_pc_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_alu_pc_valid <= 1'b0;
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r_alu_pc_valid <= 1'b0;
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else if (adf_ce) // Includes && (~alu_clear_pipeline)
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else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline)
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r_alu_pc_valid <= 1'b1;
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r_alu_pc_valid <= 1'b1;
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else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
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else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
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r_alu_pc_valid <= 1'b0;
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r_alu_pc_valid <= 1'b0;
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assign alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
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assign alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
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always @(posedge i_clk)
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always @(posedge i_clk)
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