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https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipsystem.v] - Diff between revs 98 and 113
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Rev 98 |
Rev 113 |
Line 306... |
Line 306... |
//
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//
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initial cmd_reset = 1'b1;
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initial cmd_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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//
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//
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initial cmd_halt = 1'b1;
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initial cmd_halt = START_HALTED;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
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cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
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else if (dbg_cmd_write)
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else if (dbg_cmd_write)
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cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
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cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
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else if ((cmd_step)||(cpu_break))
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else if ((cmd_step)||(cpu_break))
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cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
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initial cmd_clear_pf_cache = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
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cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
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&&((dbg_idata[11])||(dbg_idata[6]));
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&&((dbg_idata[11])||(dbg_idata[6]));
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//
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//
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initial cmd_step = 1'b0;
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initial cmd_step = 1'b0;
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