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https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
[/] [xulalx25soc/] [trunk/] [rtl/] [rtclight.v] - Diff between revs 21 and 113
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| Rev 21 |
Rev 113 |
| Line 64... |
Line 64... |
reg [21:0] clock;
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reg [21:0] clock;
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reg [31:0] stopwatch, ckspeed;
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reg [31:0] stopwatch, ckspeed;
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reg [25:0] timer;
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reg [25:0] timer;
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wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
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wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
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assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
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assign ck_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
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assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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assign tm_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
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assign sw_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
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assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
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assign al_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
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assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
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assign sp_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
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reg [39:0] ck_counter;
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reg [39:0] ck_counter;
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reg ck_carry;
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reg ck_carry;
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always @(posedge i_clk)
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always @(posedge i_clk)
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{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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