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https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
[/] [xulalx25soc/] [trunk/] [rtl/] [rxuart.v] - Diff between revs 18 and 58
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| Rev 18 |
Rev 58 |
| Line 216... |
Line 216... |
o_parity_err <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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o_frame_err <= 1'b0;
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r_setup <= i_setup;
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r_setup <= i_setup;
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end else if (state == `RXU_IDLE)
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end else if (state == `RXU_IDLE)
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begin // Idle state, independent of baud counter
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begin // Idle state, independent of baud counter
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r_setup <= i_setup;
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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baud_counter <= clocks_per_baud - 28'h01;
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baud_counter <= clocks_per_baud - 28'h01;
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if ((ck_uart == 1'b0)&&(chg_counter > half_baud))
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if ((ck_uart == 1'b0)&&(chg_counter > half_baud))
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begin
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begin
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// We are in the center of a valid start bit
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// We are in the center of a valid start bit
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