| Line 107... |
Line 107... |
.CLKOUT_PHASE_SHIFT("FIXED"),
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.CLKOUT_PHASE_SHIFT("FIXED"),
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.CLK_FEEDBACK("1X"),
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.CLK_FEEDBACK("1X"),
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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.DLL_FREQUENCY_MODE("LOW"),
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.DLL_FREQUENCY_MODE("LOW"),
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.DUTY_CYCLE_CORRECTION("TRUE"),
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.DUTY_CYCLE_CORRECTION("TRUE"),
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// At a clock of 92MHz ...
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// At a clock of 80MHz ...
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// Didn't work at -64, -70, -76 is worse than the other two
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// -56: Write works, 0x96 reads work
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// -48: Write fails, 0x0183 or 0x351 is first write that fails
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// -40: Write fails, 0x071a,176a,0x576
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// -56 was my working choice at 92 MHz
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// That would be about a 2.4ns delay from clock to
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// data.
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// Suddenly needed to shift to 80 MHz.
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// -56 no longer sort of works
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// -49 writes seem to work, reads ... not so much
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// -45 writes no longer working ??
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// Read fails @ 0x891, 0x58e, @0x3d65, @0x0aec,
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// @0x11b8, @0beb, @0x01014
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// Trying a different approach: register in i_ram_feedback_clk,
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// followed by o_ram_clk, instead of registering on
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// clk_s second. Starting build at 1857
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// Okay, so that was an error, now they are referenced to
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// intermediate_clk, and I still need to try
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// intermediate_clk_n if that doesn't work.
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// THIS NEEDS A DELAY ADJUSTMENT: WBSDRAMNG adjusted from
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// 6 to 5, and rebuild started at 1914. (finished by 1930)
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// This one has read bugs at 0x027, 0x030, 0x039, 0x021
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// etc. So we are worse.
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// (We also failed timing--I did nothing to fix that)
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//
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// tho ... even if this works, it is wrong. The data lines
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// going into wbsdramng need to be clocked on the system clock
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// on entrance. Thus, the last always@ block must clock these
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// lines on clk_s. This is fixed, and cannot change.
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// This leaves us with a couple options for clocking the first
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// always block:
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//
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// i_ram_feedback_clk, posedge (the right answer ... but
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// giving me problems)
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// clk_s pos/neg edge
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// intermediate_clk posedge (Build started at 1932)
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// Result: much worse!!
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// intermediate_clk_n posedge (delay of 6 needed, not
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// tested as a result.
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//
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//
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// This clock needs to be delayed so that what takes
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// place within the SDRAM takes place at the middle
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// of the clock interval. This is separate from all the
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// rest of the logic in the FPGA where what takes place
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// happens at the clock transition.
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//
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//
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.PHASE_SHIFT(-45),
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.PHASE_SHIFT(-45),
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.STARTUP_WAIT("TRUE")
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.STARTUP_WAIT("TRUE")
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) u1( .CLKIN(clk_s),
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) u1( .CLKIN(clk_s),
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.CLK0(ck_zero_1),
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.CLK0(ck_zero_1),
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