| Line 165... |
Line 165... |
end else if (state == `TXU_IDLE) // STATE_IDLE
|
end else if (state == `TXU_IDLE) // STATE_IDLE
|
begin
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begin
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// baud_counter <= 0;
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// baud_counter <= 0;
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r_setup <= i_setup;
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r_setup <= i_setup;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
|
|
lcl_data <= i_data;
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if ((i_wr)&&(~r_busy))
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if ((i_wr)&&(~r_busy))
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begin // Immediately start us off with a start bit
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begin // Immediately start us off with a start bit
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o_uart <= 1'b0;
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o_uart <= 1'b0;
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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case(data_bits)
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case(data_bits)
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2'b00: state <= `TXU_BIT_ZERO;
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2'b00: state <= `TXU_BIT_ZERO;
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2'b01: state <= `TXU_BIT_ONE;
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2'b01: state <= `TXU_BIT_ONE;
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2'b10: state <= `TXU_BIT_TWO;
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2'b10: state <= `TXU_BIT_TWO;
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2'b11: state <= `TXU_BIT_THREE;
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2'b11: state <= `TXU_BIT_THREE;
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endcase
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endcase
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lcl_data <= i_data;
|
|
// baud_counter <= clocks_per_baud-28'h01;
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// baud_counter <= clocks_per_baud-28'h01;
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end else begin // Stay in idle
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end else begin // Stay in idle
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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r_busy <= 0;
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r_busy <= 0;
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// lcl_data is irrelevant
|
|
// state <= state;
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// state <= state;
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end
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end
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end else begin
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end else begin
|
// One clock tick in each of these states ...
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// One clock tick in each of these states ...
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// baud_counter <= clocks_per_baud - 28'h01;
|
// baud_counter <= clocks_per_baud - 28'h01;
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| Line 225... |
Line 224... |
end
|
end
|
|
|
assign o_busy = (r_busy);
|
assign o_busy = (r_busy);
|
|
|
|
|
initial zero_baud_counter = 1'b0;
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initial zero_baud_counter = 1'b1;
|
|
initial baud_counter = 28'd80000; // 1ms
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always @(posedge i_clk)
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always @(posedge i_clk)
|
begin
|
begin
|
zero_baud_counter <= (baud_counter == 28'h01);
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zero_baud_counter <= (baud_counter == 28'h01);
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if ((i_reset)||(i_break))
|
if ((i_reset)||(i_break))
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// Give ourselves 16 bauds before being ready
|
// Give ourselves 16 bauds before being ready
|
