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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 4'hb // Unused
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// 4'hb // Unused
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// 4'hc // Unused
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// 4'hc // Unused
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// `define TXU_START 4'hd // An unused state
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// `define TXU_START 4'hd // An unused state
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`define TXU_BREAK 4'he
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`define TXU_BREAK 4'he
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`define TXU_IDLE 4'hf
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`define TXU_IDLE 4'hf
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//
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//
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module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
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module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
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input i_clk, i_reset;
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input i_clk, i_reset;
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input [29:0] i_setup;
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input [29:0] i_setup;
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input i_break;
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input i_break;
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input i_wr;
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input i_wr;
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input [7:0] i_data;
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input [7:0] i_data;
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output reg o_uart, o_busy;
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output reg o_uart;
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output wire o_busy;
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wire [27:0] clocks_per_baud, break_condition;
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wire [27:0] clocks_per_baud, break_condition;
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wire [1:0] data_bits;
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wire [1:0] data_bits;
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wire use_parity, parity_even, dblstop, fixd_parity;
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wire use_parity, parity_even, dblstop, fixd_parity;
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reg [29:0] r_setup;
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reg [29:0] r_setup;
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Line 128... |
assign parity_even = r_setup[24];
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assign parity_even = r_setup[24];
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reg [27:0] baud_counter;
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reg [27:0] baud_counter;
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reg [3:0] state;
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reg [3:0] state;
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reg [7:0] lcl_data;
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reg [7:0] lcl_data;
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reg calc_parity;
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reg calc_parity, r_busy, zero_baud_counter;
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initial o_uart = 1'b1;
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initial o_uart = 1'b1;
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initial o_busy = 1'b1;
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initial r_busy = 1'b1;
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initial state = `TXU_IDLE;
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initial state = `TXU_IDLE;
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// initial baud_counter = clocks_per_baud;
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initial lcl_data= 8'h0;
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initial calc_parity = 1'b0;
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// initial baud_counter = clocks_per_baud;//ILLEGAL--not constant
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (i_reset)
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if (i_reset)
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begin
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begin
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baud_counter <= clocks_per_baud;
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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state <= `TXU_IDLE;
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state <= `TXU_IDLE;
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lcl_data <= 8'h0;
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lcl_data <= 8'h0;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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end else if (i_break)
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end else if (i_break)
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begin
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begin
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baud_counter <= break_condition;
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o_uart <= 1'b0;
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o_uart <= 1'b0;
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state <= `TXU_BREAK;
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state <= `TXU_BREAK;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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end else if (baud_counter != 0)
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end else if (~zero_baud_counter)
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begin // o_busy needs to be set coming into here
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begin // r_busy needs to be set coming into here
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baud_counter <= baud_counter - 28'h01;
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r_busy <= 1'b1;
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o_busy <= 1'b1;
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end else if (state == `TXU_BREAK)
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end else if (state == `TXU_BREAK)
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begin
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begin
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state <= `TXU_IDLE;
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state <= `TXU_IDLE;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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// Give us two stop bits before becoming available
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baud_counter <= clocks_per_baud<<2;
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end else if (state == `TXU_IDLE) // STATE_IDLE
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end else if (state == `TXU_IDLE) // STATE_IDLE
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begin
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begin
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// baud_counter <= 0;
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// baud_counter <= 0;
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r_setup <= i_setup;
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r_setup <= i_setup;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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if ((i_wr)&&(~o_busy))
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if ((i_wr)&&(~r_busy))
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begin // Immediately start us off with a start bit
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begin // Immediately start us off with a start bit
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o_uart <= 1'b0;
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o_uart <= 1'b0;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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case(data_bits)
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case(data_bits)
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2'b00: state <= `TXU_BIT_ZERO;
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2'b00: state <= `TXU_BIT_ZERO;
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2'b01: state <= `TXU_BIT_ONE;
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2'b01: state <= `TXU_BIT_ONE;
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2'b10: state <= `TXU_BIT_TWO;
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2'b10: state <= `TXU_BIT_TWO;
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2'b11: state <= `TXU_BIT_THREE;
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2'b11: state <= `TXU_BIT_THREE;
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endcase
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endcase
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lcl_data <= i_data;
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lcl_data <= i_data;
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baud_counter <= clocks_per_baud-28'h01;
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// baud_counter <= clocks_per_baud-28'h01;
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end else begin // Stay in idle
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end else begin // Stay in idle
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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o_busy <= 0;
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r_busy <= 0;
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// lcl_data is irrelevant
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// lcl_data is irrelevant
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// state <= state;
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// state <= state;
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end
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end
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end else begin
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end else begin
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// One clock tick in each of these states ...
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// One clock tick in each of these states ...
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baud_counter <= clocks_per_baud - 28'h01;
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// baud_counter <= clocks_per_baud - 28'h01;
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o_busy <= 1'b1;
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r_busy <= 1'b1;
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if (state[3] == 0) // First 8 bits
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if (state[3] == 0) // First 8 bits
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begin
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begin
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o_uart <= lcl_data[0];
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o_uart <= lcl_data[0];
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calc_parity <= calc_parity ^ lcl_data[0];
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calc_parity <= calc_parity ^ lcl_data[0];
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if (state == `TXU_BIT_SEVEN)
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if (state == `TXU_BIT_SEVEN)
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Line 215... |
calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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end else // `TXU_SECOND_STOP and default:
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end else // `TXU_SECOND_STOP and default:
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begin
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begin
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state <= `TXU_IDLE; // Go back to idle
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state <= `TXU_IDLE; // Go back to idle
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o_uart <= 1'b1;
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o_uart <= 1'b1;
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// Still o_busy, since we need to wait
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// Still r_busy, since we need to wait
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// for the baud clock to finish counting
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// for the baud clock to finish counting
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// out this last bit.
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// out this last bit.
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end
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end
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end
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end
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end
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end
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endmodule
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assign o_busy = (r_busy);
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initial zero_baud_counter = 1'b0;
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always @(posedge i_clk)
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begin
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zero_baud_counter <= (baud_counter == 28'h01);
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if ((i_reset)||(i_break))
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// Give ourselves 16 bauds before being ready
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baud_counter <= break_condition;
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else if (~zero_baud_counter)
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baud_counter <= baud_counter - 28'h01;
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else if (state == `TXU_BREAK)
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// Give us two stop bits before becoming available
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baud_counter <= clocks_per_baud<<2;
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else if (state == `TXU_IDLE)
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begin
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if((i_wr)&&(~r_busy))
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baud_counter <= clocks_per_baud - 28'h01;
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else
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zero_baud_counter <= 1'b1;
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end else
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baud_counter <= clocks_per_baud - 28'h01;
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end
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endmodule
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No newline at end of file
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No newline at end of file
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