| Line 58... |
Line 58... |
reg [29:0] r_setup;
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reg [29:0] r_setup;
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reg r_tx_stb, rx_rdy;
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reg r_tx_stb, rx_rdy;
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reg [7:0] r_tx_data;
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reg [7:0] r_tx_data;
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initial r_setup = DEFAULT_SETUP;
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initial r_setup = DEFAULT_SETUP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(~i_wb_addr[1]))
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r_setup <= i_wb_data[29:0];
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initial r_tx_stb = 1'b0;
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_addr == 2'b10))
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begin
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begin
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case(i_wb_addr)
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// Note: there's no check for overflow here.
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2'b00: r_setup <= i_wb_data[29:0];
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// You're on your own: verify that the device
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2'b10: begin
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// isn't busy first.
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r_tx_data <= i_wb_data[7:0];
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r_tx_data <= i_wb_data[7:0];
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r_tx_stb <= 1'b1;
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r_tx_stb <= 1'b1;
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end
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default: begin end
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endcase
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end else
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end else
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r_tx_stb <= 1'b0;
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r_tx_stb <= 1'b0;
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wire rx_stb, rx_break, rx_parity_err, rx_frame_err, rx_ignored;
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wire rx_stb, rx_break, rx_parity_err, rx_frame_err;
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wire [7:0] rx_data;
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wire [7:0] rx_data;
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rxuart rxmod(i_clk, 1'b0, r_setup, i_rx_uart,
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rxuart rxmod(i_clk, 1'b0, r_setup, i_rx_uart,
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rx_stb, rx_data, rx_break,
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rx_stb, rx_data, rx_break,
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rx_parity_err, rx_frame_err, rx_ignored);
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rx_parity_err, rx_frame_err);
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wire tx_break, tx_busy;
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wire tx_break, tx_busy;
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assign tx_break = 1'b0;
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assign tx_break = 1'b0;
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txuart txmod(i_clk, 1'b0, r_setup, tx_break, r_tx_stb, r_tx_data,
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txuart txmod(i_clk, 1'b0, r_setup, tx_break, r_tx_stb, r_tx_data,
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o_tx_uart, tx_busy);
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o_tx_uart, tx_busy);
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reg [7:0] r_data;
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reg [7:0] r_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (rx_stb)
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if (rx_stb)
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r_data <= rx_data;
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r_data <= rx_data;
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initial o_wb_data = 32'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (rx_stb)
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if (rx_stb)
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rx_rdy <= (rx_rdy | rx_stb);
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rx_rdy <= (rx_rdy | rx_stb);
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| Line 97... |
Line 101... |
2'b00: o_wb_data <= { 2'b00, r_setup };
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2'b00: o_wb_data <= { 2'b00, r_setup };
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2'b01: o_wb_data <= { 2'b00, r_setup };
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2'b01: o_wb_data <= { 2'b00, r_setup };
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2'b10: o_wb_data <= { 31'h00,tx_busy };
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2'b10: o_wb_data <= { 31'h00,tx_busy };
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2'b11: begin
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2'b11: begin
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
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rx_rdy <= 1'b0;
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rx_rdy <= rx_stb;
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o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };
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o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };
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end
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end
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endcase
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endcase
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); // Read or write, we ack
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end
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end
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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assign o_rx_int = rx_stb;
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assign o_rx_int = rx_stb;
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assign o_tx_int = ~tx_busy;
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assign o_tx_int = ~tx_busy;
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