| Line 42... |
Line 42... |
//
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//
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module uartdev(i_clk, i_rx_uart, o_tx_uart,
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module uartdev(i_clk, i_rx_uart, o_tx_uart,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_rx_int, o_tx_int);
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o_rx_int, o_tx_int);
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parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd10417 };
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parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd8333 };
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input i_clk, i_rx_uart;
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input i_clk, i_rx_uart;
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output wire o_tx_uart;
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output wire o_tx_uart;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [1:0] i_wb_addr;
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input [1:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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| Line 63... |
Line 63... |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(~i_wb_addr[1]))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(~i_wb_addr[1]))
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r_setup <= i_wb_data[29:0];
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r_setup <= i_wb_data[29:0];
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initial r_tx_stb = 1'b0;
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initial r_tx_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_addr == 2'b10))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_addr == 2'b11))
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begin
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begin
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// Note: there's no check for overflow here.
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// Note: there's no check for overflow here.
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// You're on your own: verify that the device
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// You're on your own: verify that the device
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// isn't busy first.
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// isn't busy first.
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r_tx_data <= i_wb_data[7:0];
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r_tx_data <= i_wb_data[7:0];
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Line 98... |
rx_rdy <= (rx_rdy | rx_stb);
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rx_rdy <= (rx_rdy | rx_stb);
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case(i_wb_addr)
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case(i_wb_addr)
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2'b00: o_wb_data <= { 2'b00, r_setup };
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2'b00: o_wb_data <= { 2'b00, r_setup };
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2'b01: o_wb_data <= { 2'b00, r_setup };
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2'b01: o_wb_data <= { 2'b00, r_setup };
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2'b10: o_wb_data <= { 31'h00,tx_busy };
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2'b10: begin
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2'b11: begin
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
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rx_rdy <= rx_stb;
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rx_rdy <= rx_stb;
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o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };
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o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };
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end
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end
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2'b11: o_wb_data <= { 31'h00,tx_busy };
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endcase
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endcase
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); // Read or write, we ack
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); // Read or write, we ack
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end
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end
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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