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[/] [xulalx25soc/] [trunk/] [rtl/] [uartdev.v] - Diff between revs 57 and 74

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//
//
//
//
module  uartdev(i_clk, i_rx_uart, o_tx_uart,
module  uartdev(i_clk, i_rx_uart, o_tx_uart,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                o_rx_int, o_tx_int);
                o_rx_int, o_tx_int, o_debug);
        parameter       DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd8333 };
        parameter       DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd8333 };
        input                   i_clk, i_rx_uart;
        input                   i_clk, i_rx_uart;
        output  wire            o_tx_uart;
        output  wire            o_tx_uart;
        input                   i_wb_cyc, i_wb_stb, i_wb_we;
        input                   i_wb_cyc, i_wb_stb, i_wb_we;
        input           [1:0]    i_wb_addr;
        input           [1:0]    i_wb_addr;
        input           [31:0]   i_wb_data;
        input           [31:0]   i_wb_data;
        output  reg             o_wb_ack;
        output  reg             o_wb_ack;
        output  wire            o_wb_stall;
        output  wire            o_wb_stall;
        output  reg     [31:0]   o_wb_data;
        output  reg     [31:0]   o_wb_data;
        output  wire            o_rx_int, o_tx_int;
        output  wire            o_rx_int, o_tx_int;
 
        output  wire    [31:0]   o_debug;
 
 
        reg     [29:0]   r_setup;
        reg     [29:0]   r_setup;
        reg             r_tx_stb, rx_rdy;
        reg             r_tx_stb, rx_rdy;
        reg     [7:0]    r_tx_data;
        reg     [7:0]    r_tx_data;
        initial r_setup = DEFAULT_SETUP;
        initial r_setup = DEFAULT_SETUP;
Line 112... Line 113...
 
 
        assign  o_wb_stall = 1'b0;
        assign  o_wb_stall = 1'b0;
        assign  o_rx_int = rx_stb;
        assign  o_rx_int = rx_stb;
        assign  o_tx_int = ~tx_busy;
        assign  o_tx_int = ~tx_busy;
 
 
 
        assign  o_debug = { (~i_rx_uart)||(~o_tx_uart), tx_busy, i_wb_addr,
 
                        rx_break, rx_frame_err, rx_parity_err, rx_rdy,
 
                        i_wb_cyc, i_wb_stb, i_wb_we, o_wb_ack,
 
                        rx_stb, rx_data,
 
                        r_tx_stb, r_tx_data,
 
                        i_rx_uart, o_tx_uart };
endmodule
endmodule
 
 
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