| Line 105... |
Line 105... |
if (VARIABLE_RATE != 0)
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if (VARIABLE_RATE != 0)
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begin
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begin
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reg [(TIMING_BITS-1):0] r_reload_value;
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reg [(TIMING_BITS-1):0] r_reload_value;
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initial r_reload_value = DEFAULT_RELOAD;
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initial r_reload_value = DEFAULT_RELOAD;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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if ((i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
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r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
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assign w_reload_value = r_reload_value;
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assign w_reload_value = r_reload_value;
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end else begin
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end else begin
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assign w_reload_value = DEFAULT_RELOAD;
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assign w_reload_value = DEFAULT_RELOAD;
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end endgenerate
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end endgenerate
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| Line 135... |
Line 135... |
reg [15:0] next_sample;
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reg [15:0] next_sample;
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reg next_valid;
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reg next_valid;
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initial next_valid = 1'b1;
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initial next_valid = 1'b1;
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initial next_sample = 16'h8000;
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initial next_sample = 16'h8000;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
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if ((i_wb_stb)&&(i_wb_we)
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&&((~i_wb_addr)||(VARIABLE_RATE==0)))
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&&((~i_wb_addr)||(VARIABLE_RATE==0)))
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begin
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begin
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// Write with two's complement data, convert it
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// Write with two's complement data, convert it
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// internally to binary offset
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// internally to binary offset
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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| Line 172... |
Line 172... |
assign o_wb_data = { 15'h00, o_int, sample_out };
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assign o_wb_data = { 15'h00, o_int, sample_out };
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end else begin
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end else begin
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reg [31:0] r_wb_data;
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reg [31:0] r_wb_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_addr)
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if (i_wb_addr)
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r_wb_data <= w_reload_value;
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r_wb_data <= { {(32-TIMING_BITS){1'b0}}, w_reload_value };
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else
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else
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r_wb_data <= { 15'h00, o_int, sample_out };
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r_wb_data <= { 15'h00, o_int, sample_out };
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assign o_wb_data = r_wb_data;
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assign o_wb_data = r_wb_data;
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end endgenerate
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end endgenerate
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|
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_stb);
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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|
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endmodule
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endmodule
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No newline at end of file
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