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[/] [xulalx25soc/] [trunk/] [rtl/] [wbpwmaudio.v] - Diff between revs 63 and 113

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Rev 63 Rev 113
Line 105... Line 105...
        if (VARIABLE_RATE != 0)
        if (VARIABLE_RATE != 0)
        begin
        begin
                reg     [(TIMING_BITS-1):0]      r_reload_value;
                reg     [(TIMING_BITS-1):0]      r_reload_value;
                initial r_reload_value = DEFAULT_RELOAD;
                initial r_reload_value = DEFAULT_RELOAD;
                always @(posedge i_clk) // Data write
                always @(posedge i_clk) // Data write
                        if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
                        if ((i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
                                r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
                                r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
                assign  w_reload_value = r_reload_value;
                assign  w_reload_value = r_reload_value;
        end else begin
        end else begin
                assign  w_reload_value = DEFAULT_RELOAD;
                assign  w_reload_value = DEFAULT_RELOAD;
        end endgenerate
        end endgenerate
Line 135... Line 135...
        reg     [15:0]   next_sample;
        reg     [15:0]   next_sample;
        reg             next_valid;
        reg             next_valid;
        initial next_valid = 1'b1;
        initial next_valid = 1'b1;
        initial next_sample = 16'h8000;
        initial next_sample = 16'h8000;
        always @(posedge i_clk) // Data write
        always @(posedge i_clk) // Data write
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
                if ((i_wb_stb)&&(i_wb_we)
                                &&((~i_wb_addr)||(VARIABLE_RATE==0)))
                                &&((~i_wb_addr)||(VARIABLE_RATE==0)))
                begin
                begin
                        // Write with two's complement data, convert it
                        // Write with two's complement data, convert it
                        // internally to binary offset
                        // internally to binary offset
                        next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
                        next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
Line 172... Line 172...
                assign o_wb_data = { 15'h00, o_int, sample_out };
                assign o_wb_data = { 15'h00, o_int, sample_out };
        end else begin
        end else begin
                reg     [31:0]   r_wb_data;
                reg     [31:0]   r_wb_data;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_wb_addr)
                        if (i_wb_addr)
                                r_wb_data <= w_reload_value;
                                r_wb_data <= { {(32-TIMING_BITS){1'b0}}, w_reload_value };
                        else
                        else
                                r_wb_data <= { 15'h00, o_int, sample_out };
                                r_wb_data <= { 15'h00, o_int, sample_out };
                assign  o_wb_data = r_wb_data;
                assign  o_wb_data = r_wb_data;
        end endgenerate
        end endgenerate
 
 
        initial o_wb_ack = 1'b0;
        initial o_wb_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
                o_wb_ack <= (i_wb_stb);
        assign  o_wb_stall = 1'b0;
        assign  o_wb_stall = 1'b0;
 
 
endmodule
endmodule
 
 
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