| Line 82... |
Line 82... |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_pwm, o_int);
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o_pwm, o_int);
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parameter DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @ 80MHz
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parameter DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @ 80MHz
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//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
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//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
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VARIABLE_RATE=0;
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VARIABLE_RATE=1;
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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| Line 103... |
Line 103... |
if (VARIABLE_RATE != 0)
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if (VARIABLE_RATE != 0)
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begin
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begin
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reg [31:0] r_reload_value;
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reg [31:0] r_reload_value;
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initial r_reload_value = DEFAULT_RELOAD;
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initial r_reload_value = DEFAULT_RELOAD;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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reload_value <= i_wb_data;
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reload_value <= i_wb_data;
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wire [31:0] w_reload_value;
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wire [31:0] w_reload_value;
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assign w_reload_value = r_reload_value;
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assign w_reload_value = r_reload_value;
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end else begin
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end else begin
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wire [31:0] w_reload_value;
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wire [31:0] w_reload_value;
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| Line 131... |
Line 131... |
reg [15:0] next_sample;
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reg [15:0] next_sample;
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reg next_valid;
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reg next_valid;
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initial next_valid = 1'b1;
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initial next_valid = 1'b1;
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initial next_sample = 16'h8000;
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initial next_sample = 16'h8000;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&((~i_wb_addr)||(VARIABLE_RATE==0)))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
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&&((~i_wb_addr)||(VARIABLE_RATE==0)))
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begin
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begin
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// Write with two's complement data, convert it
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// Write with two's complement data, convert it
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// internally to binary offset
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// internally to binary offset
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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next_valid <= 1'b1;
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next_valid <= 1'b1;
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| Line 152... |
Line 153... |
pwm_counter <= pwm_counter + 1;
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pwm_counter <= pwm_counter + 1;
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|
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wire [15:0] br_counter;
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wire [15:0] br_counter;
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genvar k;
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genvar k;
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generate for(k=0; k<16; k=k+1)
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generate for(k=0; k<16; k=k+1)
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begin
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begin : bit_reversal_loop
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assign br_counter[k] = pwm_counter[15-k];
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assign br_counter[k] = pwm_counter[15-k];
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end endgenerate
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end endgenerate
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_pwm <= (sample_out < br_counter);
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o_pwm <= (sample_out < br_counter);
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