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[/] [xulalx25soc/] [trunk/] [rtl/] [wbpwmaudio.v] - Diff between revs 46 and 56

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Rev 46 Rev 56
Line 80... Line 80...
module  wbpwmaudio(i_clk,
module  wbpwmaudio(i_clk,
                // Wishbone interface
                // Wishbone interface
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                o_pwm, o_int);
                o_pwm, o_int);
        parameter       DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @  80MHz
        parameter       DEFAULT_RELOAD = 16'd1814, // about 44.1 kHz @  80MHz
                        //DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
                        //DEFAULT_RELOAD = 16'd2268,//about 44.1 kHz @ 100MHz
                        VARIABLE_RATE=0;
                        VARIABLE_RATE=0,
 
                        TIMING_BITS=17;
        input   i_clk;
        input   i_clk;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input           i_wb_addr;
        input           i_wb_addr;
        input   [31:0]   i_wb_data;
        input   [31:0]   i_wb_data;
        output  reg             o_wb_ack;
        output  reg             o_wb_ack;
Line 96... Line 97...
        output  reg             o_int;
        output  reg             o_int;
 
 
 
 
        // How often shall we create an interrupt?  Every reload_value clocks!
        // How often shall we create an interrupt?  Every reload_value clocks!
        // If VARIABLE_RATE==0, this value will never change and will be kept
        // If VARIABLE_RATE==0, this value will never change and will be kept
        // at the default reload rate (44.1 kHz, for a 100 MHz clock)
        // at the default reload rate (defined up top)
 
        wire    [(TIMING_BITS-1):0]      w_reload_value;
        generate
        generate
        if (VARIABLE_RATE != 0)
        if (VARIABLE_RATE != 0)
        begin
        begin
                reg     [31:0]   r_reload_value;
                reg     [(TIMING_BITS-1):0]      r_reload_value;
                initial r_reload_value = DEFAULT_RELOAD;
                initial r_reload_value = DEFAULT_RELOAD;
                always @(posedge i_clk) // Data write
                always @(posedge i_clk) // Data write
                        if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
                        if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
                                reload_value <= i_wb_data;
                                r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
                wire    [31:0]   w_reload_value;
 
                assign  w_reload_value = r_reload_value;
                assign  w_reload_value = r_reload_value;
        end else begin
        end else begin
                wire    [31:0]   w_reload_value;
 
                assign  w_reload_value = DEFAULT_RELOAD;
                assign  w_reload_value = DEFAULT_RELOAD;
        end endgenerate
        end endgenerate
 
 
        reg     [31:0]   reload_value, timer;
        reg     [(TIMING_BITS-1):0]      timer;
        initial reload_value = DEFAULT_RELOAD;
 
        initial timer = DEFAULT_RELOAD;
        initial timer = DEFAULT_RELOAD;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (timer == 0)
                if (timer == 0)
                        timer <= reload_value;
                        timer <= w_reload_value;
                else
                else
                        timer <= timer - 1;
                        timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
 
 
        reg     [15:0]   sample_out;
        reg     [15:0]   sample_out;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (timer == 0)
                if (timer == 0)
                        sample_out <= next_sample;
                        sample_out <= next_sample;
Line 149... Line 148...
                o_int <= (~next_valid);
                o_int <= (~next_valid);
 
 
        reg     [15:0]   pwm_counter;
        reg     [15:0]   pwm_counter;
        initial pwm_counter = 16'h00;
        initial pwm_counter = 16'h00;
        always @(posedge i_clk)
        always @(posedge i_clk)
                pwm_counter <= pwm_counter + 1;
                pwm_counter <= pwm_counter + 16'h01;
 
 
        wire    [15:0]   br_counter;
        wire    [15:0]   br_counter;
        genvar  k;
        genvar  k;
        generate for(k=0; k<16; k=k+1)
        generate for(k=0; k<16; k=k+1)
        begin : bit_reversal_loop
        begin : bit_reversal_loop
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                assign o_wb_data = { 15'h00, o_int, sample_out };
                assign o_wb_data = { 15'h00, o_int, sample_out };
        end else begin
        end else begin
                reg     [31:0]   r_wb_data;
                reg     [31:0]   r_wb_data;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_wb_addr)
                        if (i_wb_addr)
                                r_wb_data <= reload_value;
                                r_wb_data <= w_reload_value;
                        else
                        else
                                r_wb_data <= { 15'h00, o_int, sample_out };
                                r_wb_data <= { 15'h00, o_int, sample_out };
                assign  o_wb_data = r_wb_data;
                assign  o_wb_data = r_wb_data;
        end endgenerate
        end endgenerate
 
 

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