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module wbpwmaudio(i_clk,
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module wbpwmaudio(i_clk,
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// Wishbone interface
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_pwm, o_int);
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o_pwm, o_int);
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parameter DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @ 80MHz
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parameter DEFAULT_RELOAD = 16'd1814, // about 44.1 kHz @ 80MHz
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//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
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//DEFAULT_RELOAD = 16'd2268,//about 44.1 kHz @ 100MHz
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VARIABLE_RATE=0;
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VARIABLE_RATE=0,
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TIMING_BITS=17;
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output reg o_int;
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output reg o_int;
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// How often shall we create an interrupt? Every reload_value clocks!
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// How often shall we create an interrupt? Every reload_value clocks!
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// at the default reload rate (44.1 kHz, for a 100 MHz clock)
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// at the default reload rate (defined up top)
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wire [(TIMING_BITS-1):0] w_reload_value;
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generate
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generate
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if (VARIABLE_RATE != 0)
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if (VARIABLE_RATE != 0)
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begin
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begin
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reg [31:0] r_reload_value;
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reg [(TIMING_BITS-1):0] r_reload_value;
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initial r_reload_value = DEFAULT_RELOAD;
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initial r_reload_value = DEFAULT_RELOAD;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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reload_value <= i_wb_data;
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r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
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wire [31:0] w_reload_value;
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assign w_reload_value = r_reload_value;
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assign w_reload_value = r_reload_value;
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end else begin
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end else begin
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wire [31:0] w_reload_value;
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assign w_reload_value = DEFAULT_RELOAD;
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assign w_reload_value = DEFAULT_RELOAD;
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end endgenerate
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end endgenerate
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reg [31:0] reload_value, timer;
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reg [(TIMING_BITS-1):0] timer;
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initial reload_value = DEFAULT_RELOAD;
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initial timer = DEFAULT_RELOAD;
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initial timer = DEFAULT_RELOAD;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (timer == 0)
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if (timer == 0)
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timer <= reload_value;
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timer <= w_reload_value;
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else
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else
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timer <= timer - 1;
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timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
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reg [15:0] sample_out;
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reg [15:0] sample_out;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (timer == 0)
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if (timer == 0)
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sample_out <= next_sample;
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sample_out <= next_sample;
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o_int <= (~next_valid);
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o_int <= (~next_valid);
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reg [15:0] pwm_counter;
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reg [15:0] pwm_counter;
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initial pwm_counter = 16'h00;
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initial pwm_counter = 16'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pwm_counter <= pwm_counter + 1;
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pwm_counter <= pwm_counter + 16'h01;
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wire [15:0] br_counter;
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wire [15:0] br_counter;
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genvar k;
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genvar k;
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generate for(k=0; k<16; k=k+1)
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generate for(k=0; k<16; k=k+1)
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begin : bit_reversal_loop
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begin : bit_reversal_loop
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assign o_wb_data = { 15'h00, o_int, sample_out };
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assign o_wb_data = { 15'h00, o_int, sample_out };
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end else begin
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end else begin
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reg [31:0] r_wb_data;
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reg [31:0] r_wb_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_addr)
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if (i_wb_addr)
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r_wb_data <= reload_value;
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r_wb_data <= w_reload_value;
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else
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else
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r_wb_data <= { 15'h00, o_int, sample_out };
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r_wb_data <= { 15'h00, o_int, sample_out };
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assign o_wb_data = r_wb_data;
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assign o_wb_data = r_wb_data;
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end endgenerate
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end endgenerate
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