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//
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//
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// Filename: wbpwmaudio.v
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// Filename: wbpwmaudio.v
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//
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//
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// Project: A Wishbone Controlled PWM (audio) controller
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// Project: A Wishbone Controlled PWM (audio) controller
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//
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//
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// Purpose:
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// Purpose: This PWM controller was designed with audio in mind, although
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//
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// it should be sufficient for many other purposes. Specifically,
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//
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// it creates a pulse-width modulated output, where the amount of time
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// the output is 'high' is determined by the pulse width data given to
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// it. Further, the 'high' time is spread out in bit reversed order.
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// In this fashion, a halfway point will alternate between high and low,
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// rather than the normal fashion of being high for half the time and then
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// low. This approach was chosen to move the PWM artifacts to higher,
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// inaudible frequencies and hence improve the sound quality.
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//
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// The interface supports two addresses:
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//
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// Addr[0] is the data register. Writes to this register will set
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// a 16-bit sample value to be produced by the PWM logic.
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// Reads will also produce, in the 17th bit, whether the interrupt
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// is set or not. (If set, it's time to write a new data value
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// ...)
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//
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// Addr[1] is a timer reload value, used to determine how often the
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// PWM logic needs its next value. This number should be set
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// to the number of clock cycles between reload values. So,
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// for example, an 80 MHz clock can generate a 44.1 kHz audio
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// stream by reading in a new sample every (80e6/44.1e3 = 1814)
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// samples. After loading a sample, the device is immediately
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// ready to load a second. Once the first sample completes,
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// the second sample will start going to the output, and an
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// interrupt will be generated indicating that the device is
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// now ready for the third sample. (The one sample buffer
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// allows some flexibility in getting the new sample there fast
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// enough ...)
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//
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//
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// If you read through the code below, you'll notice that you can also
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// set the timer reload value to an immutable constant by changing the
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// VARIABLE_RATE parameter to 0. When VARIABLE_RATE is set to zero,
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// both addresses become the same, Addr[0] or the data register, and the
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// reload value can no longer be changed--forcing the sample rate to
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// stay constant.
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//
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//
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// Of course, if you don't want to deal with the interrupts or sample
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// rates, you can still get a pseudo analog output by just setting the
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// value to the analog output you would like and then not updating
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// it. In this case, you could also shut the interrupt down at the
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// controller, to keep that from bothering you as well.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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module wbpwmaudio(i_clk,
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module wbpwmaudio(i_clk,
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// Wishbone interface
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_pwm, o_int);
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o_pwm, o_int);
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parameter DEFAULT_RELOAD = 32'd2268, // about 44.1 kHz @ 80MHz
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parameter DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @ 80MHz
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//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
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//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
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VARIABLE_RATE=0;
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VARIABLE_RATE=0;
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input i_wb_addr;
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