| Line 109... |
Line 109... |
bw_disable_trigger, bw_reset_complete;
|
bw_disable_trigger, bw_reset_complete;
|
reg [22:0] br_config;
|
reg [22:0] br_config;
|
wire [19:0] bw_holdoff;
|
wire [19:0] bw_holdoff;
|
initial br_config = ((1<<(LGMEM-1))-4);
|
initial br_config = ((1<<(LGMEM-1))-4);
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr))
|
if ((i_wb_stb)&&(~i_wb_addr))
|
begin
|
begin
|
if (i_wb_we)
|
if (i_wb_we)
|
br_config <= { i_wb_data[31],
|
br_config <= { i_wb_data[31],
|
(i_wb_data[27]),
|
(i_wb_data[27]),
|
i_wb_data[26],
|
i_wb_data[26],
|
| Line 193... |
Line 193... |
reg [19:0] counter; // This is unsigned
|
reg [19:0] counter; // This is unsigned
|
initial dr_stopped = 1'b0;
|
initial dr_stopped = 1'b0;
|
initial counter = 20'h0000;
|
initial counter = 20'h0000;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dw_reset)
|
if (dw_reset)
|
begin
|
|
counter <= 0;
|
counter <= 0;
|
dr_stopped <= 1'b0;
|
else if ((i_ce)&&(dr_triggered)&&(~dr_stopped))
|
end else if ((i_ce)&&(dr_triggered))
|
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
// 20 bits. Else we'd need to add a bit to comparison
|
// 20 bits. Else we'd need to add a bit to comparison
|
// here.
|
// here.
|
if (counter < bw_holdoff)
|
|
counter <= counter + 20'h01;
|
counter <= counter + 20'h01;
|
else
|
|
dr_stopped <= 1'b1;
|
|
end
|
end
|
|
always @(posedge i_clk)
|
|
if ((~dr_triggered)||(dw_reset))
|
|
dr_stopped <= 1'b0;
|
|
else if (i_ce)
|
|
dr_stopped <= (counter+20'd1 >= bw_holdoff);
|
|
else
|
|
dr_stopped <= (counter >= bw_holdoff);
|
|
|
//
|
//
|
// Actually do our writes to memory. Record, via 'primed' when
|
// Actually do our writes to memory. Record, via 'primed' when
|
// the memory is full.
|
// the memory is full.
|
//
|
//
|
| Line 224... |
Line 226... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dw_reset) // For simulation purposes, supply a valid value
|
if (dw_reset) // For simulation purposes, supply a valid value
|
begin
|
begin
|
waddr <= 0; // upon reset.
|
waddr <= 0; // upon reset.
|
dr_primed <= 1'b0;
|
dr_primed <= 1'b0;
|
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
|
end else if ((i_ce)&&((~dr_triggered)||(~dr_stopped)))
|
begin
|
begin
|
// mem[waddr] <= i_data;
|
// mem[waddr] <= i_data;
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
dr_primed <= (dr_primed)||(&waddr);
|
dr_primed <= (dr_primed)||(&waddr);
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
|
if ((i_ce)&&((~dr_triggered)||(~dr_stopped)))
|
mem[waddr] <= i_data;
|
mem[waddr] <= i_data;
|
|
|
//
|
//
|
// Clock transfer of the status signals
|
// Clock transfer of the status signals
|
//
|
//
|
| Line 272... |
Line 274... |
|
|
// Reads use the bus clock
|
// Reads use the bus clock
|
reg br_wb_ack;
|
reg br_wb_ack;
|
initial br_wb_ack = 1'b0;
|
initial br_wb_ack = 1'b0;
|
wire bw_cyc_stb;
|
wire bw_cyc_stb;
|
assign bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb));
|
assign bw_cyc_stb = (i_wb_stb);
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
begin
|
begin
|
if ((bw_reset_request)
|
if ((bw_reset_request)
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
raddr <= 0;
|
raddr <= 0;
|
