OpenCores

Rev 2	Rev 37
Line 456...	Line 456...

`o_wb_stall <= 1'b1;`	`o_wb_stall <= 1'b1;`
`r_barrell_ack[(RDLY-1):0] <= 0;`	`r_barrell_ack[(RDLY-1):0] <= 0;`
`end`	`end`

	`ifdef VERILATOR
	`// While I hate to build something that works one way under Verilator`
	`// and another way in practice, this really isn't that. The problem`
	`// Verilator is having is resolved in toplevel.v--one file that`
	`// Verilator doesn't implement. In toplevel.v, there's not only a`
	`// single clocked latch but two taking place. Here, we replicate one`
	`// of those. The second takes place (somehow) within the sdramsim.cpp`
	`// file.`
	`reg [15:0] ram_data, last_ram_data;`
	`always @(posedge i_clk)`
	`ram_data <= i_ram_data;`
	`always @(posedge i_clk)`
	`last_ram_data <= ram_data;`
	`else
`reg [15:0] last_ram_data;`	`reg [15:0] last_ram_data;`
`always @(posedge i_clk)`	`always @(posedge i_clk)`
`last_ram_data <= i_ram_data;`	`last_ram_data <= i_ram_data;`
	`endif
`assign o_wb_ack = r_barrell_ack[0];`	`assign o_wb_ack = r_barrell_ack[0];`
`assign o_wb_data = { last_ram_data, i_ram_data };`	`assign o_wb_data = { last_ram_data, i_ram_data };`

`//`	`//`
`// The following outputs are not necessary for the functionality of`	`// The following outputs are not necessary for the functionality of`

Line 456...

                o_wb_stall  <= 1'b1;

                o_wb_stall  <= 1'b1;

                r_barrell_ack[(RDLY-1):0] <= 0;

                r_barrell_ack[(RDLY-1):0] <= 0;

end

end

`ifdef  VERILATOR

        // While I hate to build something that works one way under Verilator

        // and another way in practice, this really isn't that.  The problem

        // Verilator is having is resolved in toplevel.v--one file that

        // Verilator doesn't implement.  In toplevel.v, there's not only a

        // single clocked latch but two taking place.  Here, we replicate one

        // of those.  The second takes place (somehow) within the sdramsim.cpp

        // file.

        reg     [15:0]   ram_data, last_ram_data;

        always @(posedge i_clk)

                ram_data <= i_ram_data;

        always @(posedge i_clk)

                last_ram_data <= ram_data;

`else

        reg     [15:0]   last_ram_data;

        reg     [15:0]   last_ram_data;

        always @(posedge i_clk)

        always @(posedge i_clk)

                last_ram_data <= i_ram_data;

                last_ram_data <= i_ram_data;

`endif

        assign  o_wb_ack  = r_barrell_ack[0];

        assign  o_wb_ack  = r_barrell_ack[0];

        assign  o_wb_data = { last_ram_data, i_ram_data };

        assign  o_wb_data = { last_ram_data, i_ram_data };

//

//

        // The following outputs are not necessary for the functionality of

        // The following outputs are not necessary for the functionality of

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