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https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
[/] [xulalx25soc/] [trunk/] [rtl/] [wbsdram.v] - Diff between revs 37 and 39
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| Rev 37 |
Rev 39 |
| Line 459... |
Line 459... |
end
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end
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`ifdef VERILATOR
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`ifdef VERILATOR
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// While I hate to build something that works one way under Verilator
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// While I hate to build something that works one way under Verilator
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// and another way in practice, this really isn't that. The problem
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// and another way in practice, this really isn't that. The problem
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// Verilator is having is resolved in toplevel.v--one file that
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// \/erilator is having is resolved in toplevel.v---one file that
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// Verilator doesn't implement. In toplevel.v, there's not only a
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// \/erilator doesn't implement. In toplevel.v, there's not only a
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// single clocked latch but two taking place. Here, we replicate one
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// single clocked latch but two taking place. Here, we replicate one
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// of those. The second takes place (somehow) within the sdramsim.cpp
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// of those. The second takes place (somehow) within the sdramsim.cpp
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// file.
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// file.
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reg [15:0] ram_data, last_ram_data;
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reg [15:0] ram_data, last_ram_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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