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[/] [xulalx25soc/] [trunk/] [rtl/] [wbspiflash.v] - Diff between revs 2 and 74

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Rev 2 Rev 74
Line 89... Line 89...
                i_wb_addr, i_wb_data,
                i_wb_addr, i_wb_data,
                // Wishbone return values
                // Wishbone return values
                o_wb_ack, o_wb_stall, o_wb_data,
                o_wb_ack, o_wb_stall, o_wb_data,
                // Quad Spi connections to the external device
                // Quad Spi connections to the external device
                o_spi_sck, o_spi_cs_n, i_spi_cs_n, o_spi_mosi, i_spi_miso,
                o_spi_sck, o_spi_cs_n, i_spi_cs_n, o_spi_mosi, i_spi_miso,
                o_interrupt);
                o_interrupt,
 
                i_bus_grant);
        parameter       AW=18, // Address width, -2 for 32-bit word access
        parameter       AW=18, // Address width, -2 for 32-bit word access
                        PW=6,   // Page address width (256 bytes,64 words)
                        PW=6,   // Page address width (256 bytes,64 words)
                        SW=10;  // Sector address width (4kB, 1kW)
                        SW=10;  // Sector address width (4kB, 1kW)
        // parameter    AW, PW, Sw; // Address, page, and sector width(s)
        // parameter    AW, PW, Sw; // Address, page, and sector width(s)
        input                   i_clk_100mhz;
        input                   i_clk_100mhz;
Line 111... Line 112...
        input                   i_spi_cs_n;
        input                   i_spi_cs_n;
        output  wire            o_spi_mosi;
        output  wire            o_spi_mosi;
        input                   i_spi_miso;
        input                   i_spi_miso;
        // Interrupt line
        // Interrupt line
        output  reg             o_interrupt;
        output  reg             o_interrupt;
 
        // Do we own the bus?
 
        input                   i_bus_grant;
 
 
        // output       wire    [31:0]  o_debug;
        // output       wire    [31:0]  o_debug;
 
 
        reg             spi_wr, spi_hold;
        reg             spi_wr, spi_hold;
        reg     [31:0]   spi_in;
        reg     [31:0]   spi_in;
        reg     [1:0]    spi_len;
        reg     [1:0]    spi_len;
Line 125... Line 129...
        // wire [22:0]  spi_dbg;
        // wire [22:0]  spi_dbg;
        lldspi  lldriver(i_clk_100mhz,
        lldspi  lldriver(i_clk_100mhz,
                        spi_wr, spi_hold, spi_in, spi_len,
                        spi_wr, spi_hold, spi_in, spi_len,
                                spi_out, spi_valid, spi_busy,
                                spi_out, spi_valid, spi_busy,
                        w_spi_sck, w_spi_cs_n, i_spi_cs_n, w_spi_mosi,
                        w_spi_sck, w_spi_cs_n, i_spi_cs_n, w_spi_mosi,
                                i_spi_miso);
                                i_spi_miso,
 
                        i_bus_grant);
 
 
        // Erase status tracking
        // Erase status tracking
        reg             write_in_progress, write_protect;
        reg             write_in_progress, write_protect;
        reg [(AW-1-SW):0] erased_sector;
        reg [(AW-1-SW):0] erased_sector;
        reg             dirty_sector;
        reg             dirty_sector;

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