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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbubus.v
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// Filename: wbubus.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: This is the top level file for the entire JTAG-USB to Wishbone
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// Purpose: This is the top level file for the entire JTAG-USB to Wishbone
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// bus conversion. (It's also the place to start debugging, should
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// bus conversion. (It's also the place to start debugging, should
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// things not go as planned.) Bytes come into this routine, bytes go out,
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// things not go as planned.) Bytes come into this routine, bytes go out,
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// and the wishbone bus (external to this routine) is commanded in between.
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// and the wishbone bus (external to this routine) is commanded in between.
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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module wbubus(i_clk, i_rx_stb, i_rx_data,
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module wbubus(i_clk, i_rx_stb, i_rx_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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i_interrupt,
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i_interrupt,
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o_tx_stb, o_tx_data, i_tx_busy);
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o_tx_stb, o_tx_data, i_tx_busy, o_dbg);
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parameter LGWATCHDOG=19;
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parameter LGWATCHDOG=19;
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input i_clk;
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input i_clk;
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input i_rx_stb;
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input i_rx_stb;
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input [7:0] i_rx_data;
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input [7:0] i_rx_data;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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input i_interrupt;
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input i_interrupt;
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output wire o_tx_stb;
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output wire o_tx_stb;
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output wire [7:0] o_tx_data;
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output wire [7:0] o_tx_data;
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input i_tx_busy;
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input i_tx_busy;
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// output wire [31:0] o_dbg;
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output wire o_dbg;
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reg r_wdt_reset;
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reg r_wdt_reset;
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// Decode ASCII input requests into WB bus cycle requests
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// Decode ASCII input requests into WB bus cycle requests
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assign cyc_debug = { 1'b0, o_wb_cyc, o_wb_stb, o_wb_we, i_wb_ack, i_wb_stall,
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assign cyc_debug = { 1'b0, o_wb_cyc, o_wb_stb, o_wb_we, i_wb_ack, i_wb_stall,
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(i_wb_err||r_wdt_reset), o_wb_addr[14:0],
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(i_wb_err||r_wdt_reset), o_wb_addr[14:0],
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o_wb_data[4:0], i_wb_data[4:0] };
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o_wb_data[4:0], i_wb_data[4:0] };
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assign o_dbg = cyc_debug;
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assign o_dbg = cyc_debug;
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*/
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*/
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/*
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/*
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wire [31:0] fif_debug;
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wire [31:0] fif_debug;
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assign fif_debug = {
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assign fif_debug = {
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(exec_stb)&&(exec_word[35:30] == 6'h05),// 1
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(exec_stb)&&(exec_word[35:30] == 6'h05),// 1
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fifo_in_stb, fifo_in_word[35:30], // 7
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fifo_in_stb, fifo_in_word[35:30], // 7
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end else begin
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end else begin
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r_wdt_timer <= r_wdt_timer+{{(LGWATCHDOG-1){1'b0}},1'b1};
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r_wdt_timer <= r_wdt_timer+{{(LGWATCHDOG-1){1'b0}},1'b1};
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r_wdt_reset <= 1'b0;
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r_wdt_reset <= 1'b0;
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end
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end
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assign o_dbg = w_bus_reset;
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endmodule
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endmodule
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