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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbucompress.v
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// Filename: wbucompress.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: When reading many words that are identical, it makes no sense
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// Purpose: When reading many words that are identical, it makes no sense
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// to spend the time transmitting the same thing over and over
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// to spend the time transmitting the same thing over and over
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// again, especially on a slow channel. Hence this routine uses a table
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// again, especially on a slow channel. Hence this routine uses a table
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// lookup to see if the word to be transmitted was one from the recent
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// lookup to see if the word to be transmitted was one from the recent
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// table. And the first part of that is keeping track of what address
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// table. And the first part of that is keeping track of what address
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// to write into the compression table, and whether or not the entire
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// to write into the compression table, and whether or not the entire
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// table is full or not. This logic follows:
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// table is full or not. This logic follows:
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//
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//
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reg [(TBITS-1):0] tbl_addr;
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reg [(TBITS-1):0] tbl_addr;
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reg r_compressed, tbl_filled;
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reg tbl_filled;
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// First part, write the compression table
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// First part, write the compression table
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always @(posedge i_clk)
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always @(posedge i_clk)
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// If we send a new address, then reset the table to empty
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// If we send a new address, then reset the table to empty
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if (w_accepted)
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if (w_accepted)
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begin
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begin
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// Now that we have a working table, can we use it?
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// Now that we have a working table, can we use it?
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// On any new word, we'll start looking through our codewords.
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// On any new word, we'll start looking through our codewords.
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// If we find any that matches, we're there. We might (or might not)
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// If we find any that matches, we're there. We might (or might not)
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// make it through the table first. That's irrelevant. We just look
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// make it through the table first. That's irrelevant. We just look
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// while we can.
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// while we can.
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reg tbl_match, nxt_match; // <= (nxt_rd_addr == tbl_addr);
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reg [(TBITS-1):0] rd_addr;
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reg [(TBITS-1):0] rd_addr;
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wire [(TBITS-1):0] nxt_rd_addr;
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reg [(TBITS-1):0] nxt_rd_addr;
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assign nxt_rd_addr = rd_addr - { {(TBITS-1){1'b0}}, 1'b1 };
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initial rd_addr = 0;
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initial rd_addr = 0;
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initial tbl_match = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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nxt_match <= ((nxt_rd_addr-tbl_addr)=={{(TBITS-1){1'b0}},1'b1});
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if ((w_accepted)||(~a_stb))
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if ((w_accepted)||(~a_stb))
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begin
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// Keep in mind, if a write was just accepted, then
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// Keep in mind, if a write was just accepted, then
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// rd_addr will need to be reset on the next clock
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// rd_addr will need to be reset on the next clock
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// when (~a_stb). Hence this must be a two clock
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// when (~a_stb). Hence this must be a two clock
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// update
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// update
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rd_addr <= tbl_addr + {(TBITS){1'b1}};
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rd_addr <= tbl_addr + {(TBITS){1'b1}};
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else if ((nxt_rd_addr != tbl_addr)&&(~match)
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nxt_rd_addr = tbl_addr + { {(TBITS-1){1'b1}}, 1'b0 };
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tbl_match <= 1'b0;
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end else if ((~tbl_match)&&(~match)
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&&((~nxt_rd_addr[TBITS-1])||(tbl_filled)))
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&&((~nxt_rd_addr[TBITS-1])||(tbl_filled)))
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begin
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rd_addr <= nxt_rd_addr;
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rd_addr <= nxt_rd_addr;
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nxt_rd_addr = nxt_rd_addr - { {(TBITS-1){1'b0}}, 1'b1 };
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tbl_match <= nxt_match;
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end
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end
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reg [1:0] pmatch;
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reg dmatch, // Match, on clock 'd'
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vaddr; // Was the address valid then?
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reg [(DW-1):0] cword;
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reg [(DW-1):0] cword;
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reg [(TBITS-1):0] caddr;
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reg [(TBITS-1):0] caddr, daddr, maddr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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cword <= compression_tbl[rd_addr];
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cword <= compression_tbl[rd_addr];
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caddr <= rd_addr;
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caddr <= rd_addr;
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dmatch <= (cword == { r_word[32:31], r_word[29:0] });
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daddr <= caddr;
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maddr <= tbl_addr - caddr;
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vaddr <= ( {1'b0, caddr} < {tbl_filled, tbl_addr} )
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&&(caddr != tbl_addr);
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end
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end
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always @(posedge i_clk)
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if ((w_accepted)||(~a_stb))
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pmatch <= 0; // rd_addr is set on this clock
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else
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// cword is set on the next clock, pmatch = 3'b001
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// dmatch is set on the next clock, pmatch = 3'b011
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pmatch <= { pmatch[0], 1'b1 };
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reg match;
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reg match;
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reg [9:0] matchaddr;
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reg [9:0] matchaddr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if((w_accepted)||(~a_stb)||(~r_stb))// Reset upon any write
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if((w_accepted)||(~a_stb)||(~r_stb))// Reset upon any write
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match <= 1'b0;
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match <= 1'b0;
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else if (~match)
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else if (~match)
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begin
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begin
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// To be a match, the table must not be empty,
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// To be a match, the table must not be empty,
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match <= (({1'b0, caddr } < {tbl_filled, tbl_addr}))
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match <= (vaddr)&&(dmatch)&&(r_word[35:33]==3'b111)
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// the word we are matching to must be
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&&(pmatch == 2'b11);
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// in the form of a read command
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end
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&&(r_word[35:33] == 3'b111)
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// And the word in the table must be
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reg zmatch, hmatch, fmatch;
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// identical to the word we are about
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always @(posedge i_clk)
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// to send.
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if (~match)
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&&(cword == { r_word[32:31], r_word[29:0] });
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begin
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matchaddr <= tbl_addr-caddr;
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matchaddr <= maddr;
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fmatch <= (maddr < 10'h521);
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zmatch <= (maddr == 10'h1);
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hmatch <= (maddr < 10'd10);
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end
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end
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// Did we find something?
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// Did we find something?
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wire [(TBITS-1):0] adr_diff;
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wire [(TBITS-1):0] adr_diff;
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wire [9:0] adr_dbld;
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wire [9:0] adr_dbld;
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wire [2:0] adr_hlfd;
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wire [2:0] adr_hlfd;
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assign adr_diff = matchaddr;
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assign adr_diff = matchaddr;
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assign adr_hlfd = matchaddr[2:0]- 3'd2;
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assign adr_hlfd = matchaddr[2:0]- 3'd2;
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assign adr_dbld = matchaddr- 10'd10;
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assign adr_dbld = matchaddr- 10'd10;
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initial r_compressed = 1'b0;
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reg [(CW-1):0] r_cword; // Record our result
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reg [(CW-1):0] r_cword; // Record our result
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((~a_stb)||(~r_stb)||(w_accepted))//Reset whenever word gets written
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if ((~a_stb)||(~r_stb)||(w_accepted))//Reset whenever word gets written
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r_compressed <= 1'b0; // to our output
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else if (r_compressed)//Already compressed, wait 'til sent
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;
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else if ((match)&&(matchaddr < 10'd521)) // &&(r_word == a_addrword))
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begin
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begin
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if (matchaddr == 10'h1)
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r_cword <= r_word;
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end else if ((match)&&(fmatch)) // &&(r_word == a_addrword))
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begin
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r_cword <= r_word;
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if (zmatch) // matchaddr == 1
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r_cword[35:30] <= { 5'h3, r_word[30] };
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r_cword[35:30] <= { 5'h3, r_word[30] };
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else if (adr_diff < 10'd10)
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else if (hmatch) // 2 <= matchaddr <= 9
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r_cword[35:30] <= { 2'b10, adr_hlfd, r_word[30] };
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r_cword[35:30] <= { 2'b10, adr_hlfd, r_word[30] };
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else // if (adr_diff < 10'd521)
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else // if (adr_diff < 10'd521)
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r_cword[35:24] <= { 2'b01, adr_dbld[8:6],
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r_cword[35:24] <= { 2'b01, adr_dbld[8:6],
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r_word[30], adr_dbld[5:0] };
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r_word[30], adr_dbld[5:0] };
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r_compressed <= 1'b1;
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end else
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end else
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r_cword <= r_word;
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r_cword <= r_word;
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end
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end
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// Can we do this without a clock delay?
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// Can we do this without a clock delay?
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assign o_stb = a_stb;
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assign o_stb = a_stb;
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assign o_cword = (r_compressed)?(r_cword):(a_addrword);
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assign o_cword = (r_stb)?(r_cword):(a_addrword);
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endmodule
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endmodule
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