| Line 203... |
Line 203... |
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reg [1:0] pmatch;
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reg [1:0] pmatch;
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reg dmatch, // Match, on clock 'd'
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reg dmatch, // Match, on clock 'd'
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vaddr; // Was the address valid then?
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vaddr; // Was the address valid then?
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reg [(DW-1):0] cword;
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reg [(DW-1):0] cword;
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reg [(TBITS-1):0] caddr, daddr, maddr;
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reg [(TBITS-1):0] caddr, maddr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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cword <= compression_tbl[rd_addr];
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cword <= compression_tbl[rd_addr];
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caddr <= rd_addr;
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caddr <= rd_addr;
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dmatch <= (cword == { r_word[32:31], r_word[29:0] });
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dmatch <= (cword == { r_word[32:31], r_word[29:0] });
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daddr <= caddr;
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maddr <= tbl_addr - caddr;
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maddr <= tbl_addr - caddr;
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vaddr <= ( {1'b0, caddr} < {tbl_filled, tbl_addr} )
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vaddr <= ( {1'b0, caddr} < {tbl_filled, tbl_addr} )
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&&(caddr != tbl_addr);
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&&(caddr != tbl_addr);
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end
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end
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| Line 248... |
Line 247... |
zmatch <= (maddr == 10'h1);
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zmatch <= (maddr == 10'h1);
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hmatch <= (maddr < 10'd10);
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hmatch <= (maddr < 10'd10);
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end
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end
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// Did we find something?
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// Did we find something?
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wire [(TBITS-1):0] adr_diff;
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wire [9:0] adr_dbld;
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wire [9:0] adr_dbld;
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wire [2:0] adr_hlfd;
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wire [2:0] adr_hlfd;
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assign adr_diff = matchaddr;
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assign adr_hlfd = matchaddr[2:0]- 3'd2;
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assign adr_hlfd = matchaddr[2:0]- 3'd2;
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assign adr_dbld = matchaddr- 10'd10;
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assign adr_dbld = matchaddr- 10'd10;
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reg [(CW-1):0] r_cword; // Record our result
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reg [(CW-1):0] r_cword; // Record our result
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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