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https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
[/] [xulalx25soc/] [trunk/] [rtl/] [wbucompress.v] - Diff between revs 2 and 9
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| Rev 2 |
Rev 9 |
| Line 119... |
Line 119... |
assign w_accepted = (a_stb)&&(~i_busy);
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assign w_accepted = (a_stb)&&(~i_busy);
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reg r_stb;
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reg r_stb;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_stb <= a_stb;
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r_stb <= a_stb;
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/*
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reg [35:0] r_word;
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always @(posedge i_clk)
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if (a_stb)
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r_word <= a_addrword;
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*/
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wire [35:0] r_word;
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wire [35:0] r_word;
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assign r_word = a_addrword;
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assign r_word = a_addrword;
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//
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//
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| Line 235... |
Line 230... |
begin
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begin
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if ((~a_stb)||(~r_stb)||(w_accepted))//Reset whenever word gets written
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if ((~a_stb)||(~r_stb)||(w_accepted))//Reset whenever word gets written
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r_compressed <= 1'b0; // to our output
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r_compressed <= 1'b0; // to our output
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else if (r_compressed)//Already compressed, wait 'til sent
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else if (r_compressed)//Already compressed, wait 'til sent
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;
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;
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else if ((match)&&(matchaddr < 10'd521)&&(r_word == a_addrword))
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else if ((match)&&(matchaddr < 10'd521))
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begin
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begin
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if (matchaddr == 10'h1)
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if (matchaddr == 10'h1)
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r_cword[35:30] <= { 5'h3, r_word[30] };
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r_cword[35:30] <= { 5'h3, r_word[30] };
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else if (adr_diff < 10'd10)
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else if (adr_diff < 10'd10)
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r_cword[35:30] <= { 2'b10, adr_hlfd, r_word[30] };
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r_cword[35:30] <= { 2'b10, adr_hlfd, r_word[30] };
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