| Line 33... |
Line 33... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`define WB_IDLE 3'b000
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`define WB_READ_REQUEST 3'b001
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`define WB_WRITE_REQUEST 3'b010
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`define WB_ACK 3'b011
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`define WB_WAIT_ON_NEXT_WRITE 3'b100
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`define WB_FLUSH_WRITE_REQUESTS 3'b101
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module wbuexec(i_clk, i_rst, i_stb, i_codword, o_busy,
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module wbuexec(i_clk, i_rst, i_stb, i_codword, o_busy,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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o_stb, o_codword);
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o_stb, o_codword);
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input i_clk, i_rst;
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input i_clk, i_rst;
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// The command inputs
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// The command inputs
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input i_stb;
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input i_stb;
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input [35:0] i_codword;
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input [35:0] i_codword;
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output reg o_busy;
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output wire o_busy;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb;
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output reg o_wb_we;
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output reg [31:0] o_wb_addr, o_wb_data;
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output reg [31:0] o_wb_addr, o_wb_data;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// And our codeword outputs
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// And our codeword outputs
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| Line 63... |
Line 71... |
assign w_eow = (w_accept)&&(i_codword[35:30] == 6'h2e);
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assign w_eow = (w_accept)&&(i_codword[35:30] == 6'h2e);
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// assign w_newrd = (w_accept)&&(i_codword[35:34] == 2'b11);
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// assign w_newrd = (w_accept)&&(i_codword[35:34] == 2'b11);
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wire [31:0] w_cod_data;
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wire [31:0] w_cod_data;
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assign w_cod_data={ i_codword[32:31], i_codword[29:0] };
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assign w_cod_data={ i_codword[32:31], i_codword[29:0] };
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assign w_new_err = ((w_accept)
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assign w_new_err = ((w_accept)
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&&((i_codword[35:33] != 3'h3)||(~o_wb_we))
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&&(i_codword[35:33] != 3'h3)
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&&(i_codword[35:30] != 6'h2e));
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&&(i_codword[35:30] != 6'h2e));
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reg [2:0] wb_state;
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reg [9:0] r_acks_needed, r_len;
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reg [9:0] r_acks_needed, r_len;
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reg r_inc, r_new_addr, last_read_request, last_ack, zero_acks;
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reg r_inc, r_wb_err, r_new_addr, r_eow;
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initial r_wb_err = 1'b0;
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initial r_new_addr = 1'b1;
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initial r_new_addr = 1'b1;
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initial wb_state = `WB_IDLE;
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initial o_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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wb_state <= `WB_IDLE;
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o_stb <= 1'b1;
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o_stb <= 1'b1;
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o_codword <= { 6'h3, 30'h000 };
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o_codword <= { 6'h3, i_wb_data[29:0] };
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r_wb_err <= 1'b0;
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end else case(wb_state)
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o_wb_cyc <= 1'b0;
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`WB_IDLE: begin
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end else if (o_wb_cyc) // In the middle of a bus transaction
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// Now output codewords while we're idle,
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begin
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// ... unless we get an address command (later).
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o_stb <= 1'b0;
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o_stb <= 1'b0;
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// Deal with bus errors
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// The new instruction. The following
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if (r_wb_err)
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// don't matter if we're not running,
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begin
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// so set them any time in this state,
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if (w_eow)
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// and if we move then they'll still be
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o_wb_cyc <= 1'b0;
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// set right.
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o_wb_stb <= 1'b0;
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end else if ((i_wb_err)||(w_new_err))
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begin
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o_wb_cyc <= (~o_busy);
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o_wb_stb <= 1'b0;
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r_wb_err <= 1'b1;
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//
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//
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o_stb <= 1'b1;
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// Increment addresses?
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o_codword <= { 6'h5, 30'h0000 };
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//
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end else if ((o_wb_stb)&&(~i_wb_stall))
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// Deal with the strobe line
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begin // Strobe was accepted, busy should be '1' here
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if (r_len != 0) // read
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r_len <= r_len - 10'h01;
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else
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o_wb_stb <= 1'b0;
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if (o_wb_we)
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begin // Acknowledge a write
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o_stb <= 1'b1;
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o_codword <= { 6'h2, 30'h0000 };
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end
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if (r_inc)
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o_wb_addr <= o_wb_addr + 32'h001;
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end else if (w_newwr) begin
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r_inc <= i_codword[30];
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r_inc <= i_codword[30];
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o_wb_data <= w_cod_data;
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// Will this be a write?
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o_wb_stb <= 1'b1;
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o_wb_we <= (~i_codword[35]);
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/*
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end else if (w_newrd)
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begin // This seems good, but it would stall the bus
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// BUS ERROR!
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o_wb_cyc <= 1'b0;
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o_stb <= 1'b1;
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o_codword <= { 4'h5, 32'h0000 };
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*/
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end
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if (w_eow)
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r_eow <= 1'b1;
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if ((r_wb_err)||(i_wb_err)||(w_new_err))
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// On an error, flush any inputs ...
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o_busy <= 1'b0;
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else if ((w_eow)||(w_newwr)||(r_eow))
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// On a new command, we're busy again
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o_busy <= 1'b1;
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else if((o_wb_we)&&(o_wb_stb)&&(~i_wb_stall)&&(r_len==0))
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// Once our command completes, if it was a write
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// command, then
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o_busy <= 1'b0;
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else if ((o_wb_we)&&(~o_wb_stb))
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o_busy <= 1'b0;
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//
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// Now let's process the acknowledgements
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//
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if ((r_wb_err)||(i_wb_err))
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begin
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// Acks are irrelevant here
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end else if (r_acks_needed != 10'h00)
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begin
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if ((i_wb_ack)&&(~o_wb_we))
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begin // Return a read result
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o_stb <= 1'b1;
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o_codword <= { 3'h7, i_wb_data[31:30], r_inc,
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i_wb_data[29:0] };
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end
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if ((i_wb_ack)&&(~w_newwr))
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r_acks_needed <= r_acks_needed - 10'h001;
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else if ((~i_wb_ack)&&(w_newwr))
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r_acks_needed <= r_acks_needed + 10'h001;
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end else if (r_acks_needed == 10'h0)
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begin
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if ((~o_wb_we)||(r_eow)||(w_eow)) // End our bus cycle
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o_wb_cyc <= 1'b0;
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else if (w_newwr)
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begin
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r_acks_needed <= r_acks_needed + 10'h001;
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o_wb_data <= w_cod_data;
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end
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end
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//
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//
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//
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//
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//
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end else if (i_stb)
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//
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//
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// Our next codeword will be the new address (if there
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// is one). Set it here. The o_stb line will determine
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// if this codeword is actually sent out.
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//
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//
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o_codword <= { 4'h2, o_wb_addr };
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o_wb_we <= (i_codword[35:34] != 2'b11);
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//
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//
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// The output data is a don't care, unless we are
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// starting a write. Hence, let's always set it as
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// though we were about to start a write.
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//
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//
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o_wb_data <= w_cod_data;
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//
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//
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if (i_stb)
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begin
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begin
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// Default is not to send any codewords
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// Default is not to send any codewords
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o_stb <= 1'b0;
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// Increment addresses?
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r_inc <= i_codword[30];
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// Will this be a write?
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o_wb_we <= (~i_codword[35]);
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// Do we need to broadcast a new address?
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// Do we need to broadcast a new address?
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// r_new_addr <= 1'b0;
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// r_new_addr <= 1'b0;
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// Errors are all clear by now
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//
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r_wb_err <= 1'b0;
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casez(i_codword[35:32])
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// Need to be not-busy when o_wb_cyc is low
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4'b0000: begin // Set a new (arbitrary) address
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o_busy <= 1'b0;
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//
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r_eow <= 1'b0;
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if (i_codword[35:32] == 4'h0)
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begin // Set a new address
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r_new_addr <= 1'b1;
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r_new_addr <= 1'b1;
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o_wb_addr <= i_codword[31:0];
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o_wb_addr <= i_codword[31:0];
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end else if (i_codword[35:33] == 3'b001)
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end
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begin // Set a new relative address
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4'b001?: begin // Set a new relative address
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r_new_addr <= 1'b1;
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o_wb_addr <= o_wb_addr
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o_wb_addr <= o_wb_addr
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+ { i_codword[32:31], i_codword[29:0] };
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+ { i_codword[32:31], i_codword[29:0] };
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end
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4'b01??: begin // Start a write transaction,
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// address is alrdy set
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r_new_addr <= 1'b1;
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r_new_addr <= 1'b1;
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end else if (i_codword[35:34] == 2'b11)
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wb_state <= `WB_WRITE_REQUEST;
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begin // Start a vector read
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end
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4'b11??: begin // Start a vector read
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// Address is already set ...
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// Address is already set ...
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// This also depends upon the decoder working
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// This also depends upon the decoder working
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r_len <= i_codword[9:0] - 10'h01;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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r_acks_needed <= i_codword[9:0];
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o_busy <= 1'b1;
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if (r_new_addr)
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if (r_new_addr)
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begin
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o_stb <= 1'b1;
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o_stb <= 1'b1;
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o_codword <= { 4'h2, o_wb_addr };
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wb_state <= `WB_READ_REQUEST;
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end
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default:
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;
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endcase
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end end
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`WB_READ_REQUEST: begin
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r_new_addr <= 1'b0;
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r_new_addr <= 1'b0;
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if (i_wb_err)
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wb_state <= `WB_IDLE;
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o_stb <= (i_wb_err)||(i_wb_ack);
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if (i_wb_err)
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o_codword <= { 6'h5, i_wb_data[29:0] };
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else
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o_codword <= { 3'h7, i_wb_data[31:30], r_inc,
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i_wb_data[29:0] };
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if ((r_inc)&&(~i_wb_stall))
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o_wb_addr <= o_wb_addr + 32'h001;
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if (~i_wb_stall) // Deal with the strobe line
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begin // Strobe was accepted, busy should be '1' here
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if (last_read_request) // (r_len != 0) // read
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wb_state <= `WB_ACK;
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end end
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`WB_WRITE_REQUEST: begin
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r_new_addr <= 1'b0;
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if (i_wb_err)
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o_codword <= { 6'h5, i_wb_data[29:0] };
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else
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o_codword <= { 6'h2, i_wb_data[29:0] };
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if ((r_inc)&&(~i_wb_stall))
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o_wb_addr <= o_wb_addr + 32'h001;
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o_stb <= (i_wb_err)||(~i_wb_stall);
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// Don't need to worry about accepting anything new
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// here, since we'll always be busy while in this state.
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// Hence, we cannot accept new write requests.
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//
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if (i_wb_err)
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begin
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wb_state <= `WB_FLUSH_WRITE_REQUESTS;
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//
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end else if (~i_wb_stall)
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wb_state <= `WB_WAIT_ON_NEXT_WRITE;
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end
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`WB_ACK: begin
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r_new_addr <= 1'b0;
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//
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// No strobes are being sent out. No further
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// bus transactions are requested. We only need
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// to finish processing the last one(s) by waiting
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// for (and recording?) their acks.
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//
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// Process acknowledgements
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if (i_wb_err)
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o_codword <= { 6'h5, i_wb_data[29:0] };
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else
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o_codword <= { 3'h7, i_wb_data[31:30], r_inc,
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i_wb_data[29:0] };
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// Return a read result, or (possibly) an error
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// notification
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o_stb <= (((i_wb_ack)&&(~o_wb_we)) || (i_wb_err));
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if (((last_ack)&&(i_wb_ack))||(zero_acks)||(i_wb_err))
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wb_state <= `WB_IDLE;
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end
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end
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end else if (~i_codword[35])
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`WB_WAIT_ON_NEXT_WRITE: begin
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begin // Start a write transaction, address is alrdy set
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r_new_addr <= 1'b0;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_codword <= { 6'h5, i_wb_data[29:0] };
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o_stb <= (i_wb_err)||(w_new_err);
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o_wb_data <= w_cod_data;
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o_wb_data <= w_cod_data;
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o_busy <= 1'b1;
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r_len <= 10'h00;
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if (w_new_err) // Something other than a write or EOW
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r_new_addr <= 1'b1;
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wb_state <= `WB_IDLE;
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r_acks_needed <= 10'h01;
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else if (i_wb_err) // Bus returns an error
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wb_state <= `WB_FLUSH_WRITE_REQUESTS;
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else if (w_newwr) // Need to make a new write request
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wb_state <= `WB_WRITE_REQUEST;
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else if (w_eow) // All done writing, wait for last ack
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wb_state <= `WB_ACK;
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end
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end
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end else begin
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`WB_FLUSH_WRITE_REQUESTS: begin
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r_wb_err <= 1'b0;
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// We come in here after an error within a write
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o_busy <= 1'b0;
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// We need to wait until the command cycle finishes
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o_stb <= 1'b0;
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// issuing all its write commands before we can go back
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// to idle.
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//
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// In the off chance that we are in here in error, or
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// out of sync, we'll transition to WB_IDLE and just
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// issue a second error token.
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r_new_addr <= 1'b0;
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o_codword <= { 6'h5, i_wb_data[29:0] };
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o_stb <= (w_new_err);
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if ((w_eow)||(w_new_err))
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wb_state <= `WB_IDLE;
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end
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default: begin
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o_stb <= 1'b1;
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o_codword <= { 6'h3, i_wb_data[29:0] };
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wb_state <= `WB_IDLE;
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end
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end
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endcase
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assign o_busy = (wb_state != `WB_IDLE)
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&&(wb_state != `WB_WAIT_ON_NEXT_WRITE)
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&&(wb_state != `WB_FLUSH_WRITE_REQUESTS);
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assign o_wb_cyc = (wb_state == `WB_READ_REQUEST)
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||(wb_state == `WB_WRITE_REQUEST)
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||(wb_state == `WB_ACK)
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||(wb_state == `WB_WAIT_ON_NEXT_WRITE);
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assign o_wb_stb = (wb_state == `WB_READ_REQUEST)
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||(wb_state == `WB_WRITE_REQUEST);
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always @(posedge i_clk)
|
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if (wb_state == `WB_IDLE)
|
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r_acks_needed <= 10'h00; // (i_codword[35])?i_codword[9:0]:10'h00;
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else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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r_acks_needed <= r_acks_needed + 10'h01;
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else if (((~o_wb_stb)||(i_wb_stall))&&(i_wb_ack))
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r_acks_needed <= r_acks_needed - 10'h01;
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|
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always @(posedge i_clk)
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last_ack <= (~o_wb_stb)&&(r_acks_needed == 10'h01);
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always @(posedge i_clk)
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zero_acks <= (~o_wb_stb)&&(r_acks_needed == 10'h00);
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always @(posedge i_clk)
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if ((wb_state == `WB_IDLE)&&(i_codword[35:34] == 2'b11))
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r_len <= i_codword[9:0] - 10'h01;
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else if ((o_wb_stb)&&(~i_wb_stall)&&(|r_len))
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r_len <= r_len - 10'h01;
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always @(posedge i_clk)
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last_read_request <= (r_len[9:0] == 10'h000);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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