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[/] [xulalx25soc/] [trunk/] [rtl/] [wbufifo.v] - Diff between revs 102 and 113

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Rev 102 Rev 113
Line 43... Line 43...
        output  wire            o_err;
        output  wire            o_err;
 
 
        reg     [(BW-1):0]       fifo[0:(FLEN-1)];
        reg     [(BW-1):0]       fifo[0:(FLEN-1)];
        reg     [(LGFLEN-1):0]   r_first, r_last;
        reg     [(LGFLEN-1):0]   r_first, r_last;
 
 
 
        wire    [(LGFLEN-1):0]   nxt_first;
 
        assign  nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
 
 
        reg     will_overflow;
        reg     will_overflow;
        initial will_overflow = 1'b0;
        initial will_overflow = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        will_overflow <= 1'b0;
                        will_overflow <= 1'b0;
                else if (i_rd)
                else if (i_rd)
                        will_overflow <= (will_overflow)&&(i_wr);
                        will_overflow <= (will_overflow)&&(i_wr);
                else if (i_wr)
                else if (i_wr)
                        will_overflow <= (r_first+2 == r_last);
                        will_overflow <= (r_first+2 == r_last);
                else if (r_first+1 == r_last)
                else if (nxt_first == r_last)
                        will_overflow <= 1'b1;
                        will_overflow <= 1'b1;
 
 
        // Write
        // Write
        initial r_first = 0;
        initial r_first = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_first <= { (LGFLEN){1'b0} };
                        r_first <= { (LGFLEN){1'b0} };
                else if (i_wr)
                else if (i_wr)
                begin // Cowardly refuse to overflow
                begin // Cowardly refuse to overflow
                        if ((i_rd)||(~will_overflow)) // (r_first+1 != r_last)
                        if ((i_rd)||(~will_overflow)) // (r_first+1 != r_last)
                                r_first <= r_first+{{(LGFLEN-1){1'b0}},1'b1};
                                r_first <= nxt_first;
                        // else o_ovfl <= 1'b1;
                        // else o_ovfl <= 1'b1;
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_wr) // Write our new value regardless--on overflow or not
                if (i_wr) // Write our new value regardless--on overflow or not
                        fifo[r_first] <= i_data;
                        fifo[r_first] <= i_data;
Line 112... Line 115...
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
                o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
                                        :(r_last)];
                                        :(r_last)];
 
 
        wire    [(LGFLEN-1):0]   nxt_first;
 
        assign  nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
 
        assign  o_err = ((i_wr)&&(will_overflow)&&(~i_rd))
        assign  o_err = ((i_wr)&&(will_overflow)&&(~i_rd))
                                ||((i_rd)&&(will_underflow)&&(~i_wr));
                                ||((i_rd)&&(will_underflow)&&(~i_wr));
 
 
        // wire [(LGFLEN-1):0]  fill;
        // wire [(LGFLEN-1):0]  fill;
        // assign       fill = (r_first-r_last);
        // assign       fill = (r_first-r_last);

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