| Line 43... |
Line 43... |
output wire o_err;
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output wire o_err;
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(LGFLEN-1):0] r_first, r_last;
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reg [(LGFLEN-1):0] r_first, r_last;
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reg will_overflow;
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initial will_overflow = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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will_overflow <= 1'b0;
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else if (i_rd)
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will_overflow <= (will_overflow)&&(i_wr);
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else if (i_wr)
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will_overflow <= (r_first+2 == r_last);
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else if (r_first+1 == r_last)
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will_overflow <= 1'b1;
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// Write
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// Write
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initial r_first = 0;
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initial r_first = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_first <= { (LGFLEN){1'b0} };
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r_first <= { (LGFLEN){1'b0} };
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else if (i_wr)
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else if (i_wr)
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begin // Cowardly refuse to overflow
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begin // Cowardly refuse to overflow
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if (r_first+1 != r_last)
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if ((i_rd)||(~will_overflow)) // (r_first+1 != r_last)
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r_first <= r_first+{{(LGFLEN-1){1'b0}},1'b1};
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r_first <= r_first+{{(LGFLEN-1){1'b0}},1'b1};
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// else o_ovfl <= 1'b1;
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// else o_ovfl <= 1'b1;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wr) // Write our new value regardless--on overflow or not
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if (i_wr) // Write our new value regardless--on overflow or not
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fifo[r_first] <= i_data;
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fifo[r_first] <= i_data;
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initial r_last = 0;
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// Reads
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// Reads
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// Following a read, the next sample will be available on the
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// Following a read, the next sample will be available on the
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// next clock
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// next clock
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// Clock ReadCMD ReadAddr Output
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// Clock ReadCMD ReadAddr Output
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// 0 0 0 fifo[0]
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// 0 0 0 fifo[0]
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| Line 71... |
Line 82... |
// 3 0 1 fifo[1]
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// 3 0 1 fifo[1]
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// 4 1 1 fifo[1]
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// 4 1 1 fifo[1]
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// 5 1 2 fifo[2]
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// 5 1 2 fifo[2]
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// 6 0 3 fifo[3]
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// 6 0 3 fifo[3]
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// 7 0 3 fifo[3]
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// 7 0 3 fifo[3]
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reg will_underflow;
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initial will_underflow = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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will_underflow <= 1'b0;
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else if (i_wr)
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will_underflow <= (will_underflow)&&(i_rd);
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else if (i_rd)
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will_underflow <= (r_last+1==r_first);
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else
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will_underflow <= (r_last == r_first);
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initial r_last = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_last <= { (LGFLEN){1'b0} };
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r_last <= { (LGFLEN){1'b0} };
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else if (i_rd)
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else if (i_rd)
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begin
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begin
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if (r_first != r_last)
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if ((i_wr)||(~will_underflow)) // (r_first != r_last)
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r_last <= r_last+{{(LGFLEN-1){1'b0}},1'b1};
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r_last <= r_last+{{(LGFLEN-1){1'b0}},1'b1};
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// Last chases first
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// Last chases first
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// Need to be prepared for a possible two
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// Need to be prepared for a possible two
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// reads in quick succession
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// reads in quick succession
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// o_data <= fifo[r_last+1];
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// o_data <= fifo[r_last+1];
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| Line 90... |
Line 114... |
o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
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o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
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:(r_last)];
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:(r_last)];
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wire [(LGFLEN-1):0] nxt_first;
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wire [(LGFLEN-1):0] nxt_first;
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assign nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
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assign nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
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assign o_err = ((i_wr)&&(nxt_first == r_last))
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assign o_err = ((i_wr)&&(will_overflow)&&(~i_rd))
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||((i_rd)&&(r_first == r_last));
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||((i_rd)&&(will_underflow)&&(~i_wr));
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// wire [(LGFLEN-1):0] fill;
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// wire [(LGFLEN-1):0] fill;
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// assign fill = (r_first-r_last);
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// assign fill = (r_first-r_last);
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wire [(LGFLEN-1):0] nxt_last;
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wire [(LGFLEN-1):0] nxt_last;
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assign nxt_last = r_last+{{(LGFLEN-1){1'b0}},1'b1};
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assign nxt_last = r_last+{{(LGFLEN-1){1'b0}},1'b1};
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