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[/] [xulalx25soc/] [trunk/] [rtl/] [wbufifo.v] - Diff between revs 2 and 59

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Rev 2 Rev 59
Line 43... Line 43...
        output  wire            o_err;
        output  wire            o_err;
 
 
        reg     [(BW-1):0]       fifo[0:(FLEN-1)];
        reg     [(BW-1):0]       fifo[0:(FLEN-1)];
        reg     [(LGFLEN-1):0]   r_first, r_last;
        reg     [(LGFLEN-1):0]   r_first, r_last;
 
 
 
        reg     will_overflow;
 
        initial will_overflow = 1'b0;
 
        always @(posedge i_clk)
 
                if (i_rst)
 
                        will_overflow <= 1'b0;
 
                else if (i_rd)
 
                        will_overflow <= (will_overflow)&&(i_wr);
 
                else if (i_wr)
 
                        will_overflow <= (r_first+2 == r_last);
 
                else if (r_first+1 == r_last)
 
                        will_overflow <= 1'b1;
 
 
        // Write
        // Write
        initial r_first = 0;
        initial r_first = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_first <= { (LGFLEN){1'b0} };
                        r_first <= { (LGFLEN){1'b0} };
                else if (i_wr)
                else if (i_wr)
                begin // Cowardly refuse to overflow
                begin // Cowardly refuse to overflow
                        if (r_first+1 != r_last)
                        if ((i_rd)||(~will_overflow)) // (r_first+1 != r_last)
                                r_first <= r_first+{{(LGFLEN-1){1'b0}},1'b1};
                                r_first <= r_first+{{(LGFLEN-1){1'b0}},1'b1};
                        // else o_ovfl <= 1'b1;
                        // else o_ovfl <= 1'b1;
                end
                end
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_wr) // Write our new value regardless--on overflow or not
                if (i_wr) // Write our new value regardless--on overflow or not
                        fifo[r_first] <= i_data;
                        fifo[r_first] <= i_data;
 
 
        initial r_last = 0;
 
        // Reads
        // Reads
        //      Following a read, the next sample will be available on the
        //      Following a read, the next sample will be available on the
        //      next clock
        //      next clock
        //      Clock   ReadCMD ReadAddr        Output
        //      Clock   ReadCMD ReadAddr        Output
        //      0        0        0                fifo[0]
        //      0        0        0                fifo[0]
Line 71... Line 82...
        //      3       0        1               fifo[1]
        //      3       0        1               fifo[1]
        //      4       1       1               fifo[1]
        //      4       1       1               fifo[1]
        //      5       1       2               fifo[2]
        //      5       1       2               fifo[2]
        //      6       0        3               fifo[3]
        //      6       0        3               fifo[3]
        //      7       0        3               fifo[3]
        //      7       0        3               fifo[3]
 
        reg     will_underflow;
 
        initial will_underflow = 1'b0;
 
        always @(posedge i_clk)
 
                if (i_rst)
 
                        will_underflow <= 1'b0;
 
                else if (i_wr)
 
                        will_underflow <= (will_underflow)&&(i_rd);
 
                else if (i_rd)
 
                        will_underflow <= (r_last+1==r_first);
 
                else
 
                        will_underflow <= (r_last == r_first);
 
 
 
        initial r_last = 0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_last <= { (LGFLEN){1'b0} };
                        r_last <= { (LGFLEN){1'b0} };
                else if (i_rd)
                else if (i_rd)
                begin
                begin
                        if (r_first != r_last)
                        if ((i_wr)||(~will_underflow)) // (r_first != r_last)
                                r_last <= r_last+{{(LGFLEN-1){1'b0}},1'b1};
                                r_last <= r_last+{{(LGFLEN-1){1'b0}},1'b1};
                                // Last chases first
                                // Last chases first
                                // Need to be prepared for a possible two
                                // Need to be prepared for a possible two
                                // reads in quick succession
                                // reads in quick succession
                                // o_data <= fifo[r_last+1];
                                // o_data <= fifo[r_last+1];
Line 90... Line 114...
                o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
                o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
                                        :(r_last)];
                                        :(r_last)];
 
 
        wire    [(LGFLEN-1):0]   nxt_first;
        wire    [(LGFLEN-1):0]   nxt_first;
        assign  nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
        assign  nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
        assign  o_err = ((i_wr)&&(nxt_first == r_last))
        assign  o_err = ((i_wr)&&(will_overflow)&&(~i_rd))
                                ||((i_rd)&&(r_first == r_last));
                                ||((i_rd)&&(will_underflow)&&(~i_wr));
 
 
        // wire [(LGFLEN-1):0]  fill;
        // wire [(LGFLEN-1):0]  fill;
        // assign       fill = (r_first-r_last);
        // assign       fill = (r_first-r_last);
        wire    [(LGFLEN-1):0]   nxt_last;
        wire    [(LGFLEN-1):0]   nxt_last;
        assign  nxt_last = r_last+{{(LGFLEN-1){1'b0}},1'b1};
        assign  nxt_last = r_last+{{(LGFLEN-1){1'b0}},1'b1};

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