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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbuidleint.v
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// Filename: wbuidleint.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: Creates an output for the interface, inserting idle words and
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// Purpose: Creates an output for the interface, inserting idle words and
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// words indicating an interrupt has taken place into the output
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// words indicating an interrupt has taken place into the output
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// stream. Henceforth, the output means more than just bus transaction
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// stream. Henceforth, the output means more than just bus transaction
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// results. It may mean there is no bus transaction result to report,
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// results. It may mean there is no bus transaction result to report,
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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