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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: cfgscope.cpp
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// Filename: cfgscope.cpp
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//
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//
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// Project: FPGA library development (Basys-3 development board)
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// Project: XuLA2 board
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//
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//
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// Purpose: To read out, and decompose, the results of the wishbone scope
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// Purpose: To read out, and decompose, the results of the wishbone scope
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// as applied to the ICAPE2 interaction.
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// as applied to the ICAPE interaction on a SPARTAN6.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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//
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// Creator: Dan Gisselquist
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// License: GPL, v3, as defined and found on www.gnu.org,
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// Gisselquist Tecnology, LLC
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright: 2015
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//
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//
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//
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//
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#include <stdio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <unistd.h>
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#include <ctype.h>
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#include <ctype.h>
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#include <string.h>
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#include <string.h>
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#include <signal.h>
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#include <signal.h>
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#include <assert.h>
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#include <assert.h>
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#include "port.h"
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#include "llcomms.h"
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#include "llcomms.h"
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#include "usbi.h"
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#include "port.h"
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#include "regdefs.h"
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#include "regdefs.h"
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#define WBSCOPE R_CFGSCOPE
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#define WBSCOPE R_CFGSCOPE
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#define WBSCOPEDATA R_CFGSCOPED
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#define WBSCOPEDATA R_CFGSCOPED
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r |= brev((v>>8)&0x0ff)<<8;
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r |= brev((v>>8)&0x0ff)<<8;
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return r;
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return r;
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}
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}
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int main(int argc, char **argv) {
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int main(int argc, char **argv) {
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FPGAOPEN(m_fpga);
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int skp=0, port = FPGAPORT;
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bool use_usb = true;
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skp=1;
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for(int argn=0; argn<argc-skp; argn++) {
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if (argv[argn+skp][0] == '-') {
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if (argv[argn+skp][1] == 'u')
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use_usb = true;
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else if (argv[argn+skp][1] == 'p') {
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use_usb = false;
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if (isdigit(argv[argn+skp][2]))
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port = atoi(&argv[argn+skp][2]);
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}
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skp++; argn--;
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} else
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argv[argn] = argv[argn+skp];
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} argc -= skp;
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if (use_usb)
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m_fpga = new FPGA(new USBI());
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else
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m_fpga = new FPGA(new NETCOMMS(FPGAHOST, port));
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signal(SIGSTOP, closeup);
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signal(SIGSTOP, closeup);
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signal(SIGHUP, closeup);
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signal(SIGHUP, closeup);
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unsigned v, lgln, scoplen;
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unsigned v, lgln, scoplen;
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printf("Attempting to read address %08x\n", WBSCOPE);
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v = m_fpga->readio(WBSCOPE);
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v = m_fpga->readio(WBSCOPE);
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if (0x60000000 != (v & 0x60000000)) {
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if (0x60000000 != (v & 0x60000000)) {
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printf("Scope is not yet ready:\n");
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printf("Scope is not yet ready:\n");
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printf("\tRESET:\t\t%s\n", (v&0x80000000)?"Ongoing":"Complete");
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printf("\tRESET:\t\t%s\n", (v&0x80000000)?"Ongoing":"Complete");
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printf("\tSTOPPED:\t%s\n", (v&0x40000000)?"Yes":"No");
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printf("\tSTOPPED:\t%s\n", (v&0x40000000)?"Yes":"No");
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DEVBUS::BUSW *buf;
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DEVBUS::BUSW *buf;
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buf = new DEVBUS::BUSW[scoplen];
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buf = new DEVBUS::BUSW[scoplen];
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if (false) {
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if (false) {
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printf("Attempting vector read\n");
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m_fpga->readz(WBSCOPEDATA, scoplen, buf);
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m_fpga->readz(WBSCOPEDATA, scoplen, buf);
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printf("Vector read complete\n");
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} else {
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} else {
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for(unsigned int i=0; i<scoplen; i++)
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for(unsigned int i=0; i<scoplen; i++)
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buf[i] = m_fpga->readio(WBSCOPEDATA);
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buf[i] = m_fpga->readio(WBSCOPEDATA);
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}
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}
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}
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}
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if (m_fpga->poll()) {
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if (m_fpga->poll()) {
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printf("FPGA was interrupted\n");
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printf("FPGA was interrupted\n");
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m_fpga->clear();
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m_fpga->clear();
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m_fpga->writeio(R_ICONTROL, SCOPEN);
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}
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}
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delete m_fpga;
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delete m_fpga;
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}
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}
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No newline at end of file
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No newline at end of file
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