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Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [sw/] [devbus.h] - Diff between revs 5 and 49

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Rev 5 Rev 49
Line 62... Line 62...
 
 
        virtual void    kill(void) = 0;
        virtual void    kill(void) = 0;
        virtual void    close(void) = 0;
        virtual void    close(void) = 0;
 
 
        // Write a single value to a single address
        // Write a single value to a single address
 
        //      a is the address of the value to be read as it exists on the
 
        //              wishbone bus within the FPGA.
 
        //      v is the singular value to write to this address
        virtual void    writeio(const BUSW a, const BUSW v) = 0;
        virtual void    writeio(const BUSW a, const BUSW v) = 0;
 
 
        // Read a single value to a single address
        // Read a single value to a single address
 
        //      a is the address of the value to be read as it exists on the
 
        //              wishbone bus within the FPGA.
 
        //      This function returns the value read from the device wishbone
 
        //              at address a.
        virtual BUSW    readio(const BUSW a) = 0;
        virtual BUSW    readio(const BUSW a) = 0;
 
 
        // Read a series of values from values from a block of memory
        // Read a series of values from values from a block of memory
 
        //      a is the address of the value to be read as it exists on the
 
        //              wishbone bus within the FPGA.
 
        //      len is the number of words to read
 
        //      buf is a pointer to a place to store the words once read.
 
        // This is equivalent to:
 
        //      for(int i=0; i<len; i++)
 
        //              buf[i] = readio(a+i);
 
        // only it's faster in our implementation.
        virtual void    readi(const BUSW a, const int len, BUSW *buf) = 0;
        virtual void    readi(const BUSW a, const int len, BUSW *buf) = 0;
 
 
        // Read a series of values from the same address in memory
        // Read a series of values from the same address in memory.  This 
 
        // call is identical to readi, save that the address is not incremented
 
        // from one read to the next.  It is equivalent to:
 
        //      for(int i=0; i<len; i++)
 
        //              buf[i] = readio(a);
 
        // only it's faster in our implementation.
 
        //
        virtual void    readz(const BUSW a, const int len, BUSW *buf) = 0;
        virtual void    readz(const BUSW a, const int len, BUSW *buf) = 0;
 
 
 
        // Write a series of values into a block of memory on the FPGA
 
        //      a is the address of the value to be written as it exists on the
 
        //              wishbone bus within the FPGA.
 
        //      len is the number of words to write
 
        //      buf is a pointer to a place to from whence to grab the data
 
        //              to be written.
 
        // This is equivalent to:
 
        //      for(int i=0; i<len; i++)
 
        //              writeio(a+i, buf[i]);
 
        // only it's faster in our implementation.
        virtual void    writei(const BUSW a, const int len, const BUSW *buf) = 0;
        virtual void    writei(const BUSW a, const int len, const BUSW *buf) = 0;
 
        // Write a series of values into the same address on the FPGA bus.  This
 
        // call is identical to writei, save that the address is not incremented
 
        // from one write to the next.  It is equivalent to:
 
        //      for(int i=0; i<len; i++)
 
        //              writeio(a, buf[i]);
 
        // only it's faster in our implementation.
 
        //
        virtual void    writez(const BUSW a, const int len, const BUSW *buf) = 0;
        virtual void    writez(const BUSW a, const int len, const BUSW *buf) = 0;
 
 
        // Query whether or not an interrupt has taken place
        // Query whether or not an interrupt has taken place
        virtual bool    poll(void) = 0;
        virtual bool    poll(void) = 0;
 
 

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