Line 21... |
Line 21... |
// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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Line 509... |
Line 509... |
m_fpga->writei(a, 128, zbuf);
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m_fpga->writei(a, 128, zbuf);
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break;
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break;
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}
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}
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} m_fpga->readio(R_VERSION); // Check for buserrors
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} m_fpga->readio(R_VERSION); // Check for buserrors
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printf("Loading memory\n");
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for(int i=0; secpp[i]->m_len; i++) {
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for(int i=0; secpp[i]->m_len; i++) {
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bool inflash=false;
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bool inflash=false;
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secp = secpp[i];
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secp = secpp[i];
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if ((secp->m_start >= SPIFLASH)
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if ((secp->m_start >= SPIFLASH)
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Line 521... |
Line 522... |
inflash = true;
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inflash = true;
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if (inflash) {
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if (inflash) {
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if (!flash)
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if (!flash)
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flash = new FLASHDRVR(m_fpga);
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flash = new FLASHDRVR(m_fpga);
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flash->write(secp->m_start, secp->m_len, secp->m_data, true);
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flash->write(secp->m_start, secp->m_len, secp->m_data, true);
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} else
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} else if (secp->m_len < (1<<16)) {
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m_fpga->writei(secp->m_start, secp->m_len, secp->m_data);
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m_fpga->writei(secp->m_start, secp->m_len, secp->m_data);
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} else {
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// The load amount is so big, we'd like to let
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// the user know where we're at along the way.
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for(unsigned k=0; k<secp->m_len; k+=(1<<16)) {
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unsigned ln = (1<<16),
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st = secp->m_start+k;
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if (st+ln > secp->m_start+secp->m_len)
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ln = (secp->m_start+secp->m_len-st);
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if (ln <= 0) break;
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printf("Loading MEM[%08x]-MEM[%08x] ...\r",
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st,st+ln-1); fflush(stdout);
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m_fpga->writei(st, ln, &secp->m_data[k]);
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m_fpga->readio(R_VERSION); // Check for buserrors
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} printf("Loaded MEM[%08x]-MEM[%08x] \n",
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secp->m_start,
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secp->m_start+secp->m_len-1);
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fflush(stdout);
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}
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printf("%08x - %08x\n", secp->m_start, secp->m_start+secp->m_len);
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}
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}
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m_fpga->readio(R_ZIPCTRL); // Check for bus errors
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m_fpga->readio(R_ZIPCTRL); // Check for bus errors
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|
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// Clear any buffers
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// Clear any buffers
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printf("Clearing the cache\n");
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printf("Clearing the cache\n");
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Line 551... |
Line 571... |
m_fpga->writeio(R_ZIPDATA, entry);
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m_fpga->writeio(R_ZIPDATA, entry);
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|
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printf("The CPU should be fully loaded, you may now start\n");
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printf("The CPU should be fully loaded, you may now start\n");
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printf("it. To start the CPU, type wbregs cpu 0\n");
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printf("it. To start the CPU, type wbregs cpu 0\n");
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} catch(BUSERR a) {
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} catch(BUSERR a) {
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fprintf(stderr, "XULA-BUS error\n");
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fprintf(stderr, "\nXULA-BUS error @0x%08x\n", a.addr);
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m_fpga->writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT|CPU_CLRCACHE);
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m_fpga->writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT|CPU_CLRCACHE);
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exit(-2);
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exit(-2);
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}
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}
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delete m_fpga;
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delete m_fpga;
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