| Line 9... |
Line 9... |
intr_reg, page_reg, par_bit, sign_bit, tflg_reg, vector_int, xhlt_reg,
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intr_reg, page_reg, par_bit, sign_bit, tflg_reg, vector_int, xhlt_reg,
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zero_bit, add_sel, alua_sel, alub_sel, aluop_sel, clearb, clkc, cflg_en,
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zero_bit, add_sel, alua_sel, alub_sel, aluop_sel, clearb, clkc, cflg_en,
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data_in, di_ctl, dma_req, do_ctl, ex_af_pls, ex_bank_pls, ex_dehl_inst,
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data_in, di_ctl, dma_req, do_ctl, ex_af_pls, ex_bank_pls, ex_dehl_inst,
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hflg_ctl, ief_ctl, imd_ctl, int_req, ivec_rd, ld_ctrl, ld_inst, ld_page,
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hflg_ctl, ief_ctl, imd_ctl, int_req, ivec_rd, ld_ctrl, ld_inst, ld_page,
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nflg_ctl, nmi_req, page_sel, pc_sel, pflg_ctl, resetb, sflg_en, tflg_ctl,
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nflg_ctl, nmi_req, page_sel, pc_sel, pflg_ctl, resetb, sflg_en, tflg_ctl,
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wait_st, wr_addr, zflg_en);
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wait_st, wr_addr, zflg_en, rreg_en);
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|
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input cflg_en; /* carry flag control */
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input cflg_en; /* carry flag control */
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input clearb; /* master (testing) reset */
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input clearb; /* master (testing) reset */
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input clkc; /* main cpu clock */
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input clkc; /* main cpu clock */
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input dma_req; /* dma request */
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input dma_req; /* dma request */
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| Line 25... |
Line 25... |
input ld_ctrl; /* load control register */
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input ld_ctrl; /* load control register */
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input ld_inst; /* load instruction register */
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input ld_inst; /* load instruction register */
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input ld_page; /* load page register */
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input ld_page; /* load page register */
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input nmi_req; /* nmi request */
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input nmi_req; /* nmi request */
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input resetb; /* internal (user) reset */
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input resetb; /* internal (user) reset */
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input rreg_en; /* update R register */
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input sflg_en; /* sign flag control */
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input sflg_en; /* sign flag control */
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input wait_st; /* wait state identifier */
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input wait_st; /* wait state identifier */
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input zflg_en; /* zero flag control */
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input zflg_en; /* zero flag control */
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input [3:0] page_sel; /* instruction decode "page" control */
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input [3:0] page_sel; /* instruction decode "page" control */
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input [7:0] data_in; /* read data bus */
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input [7:0] data_in; /* read data bus */
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| Line 89... |
Line 90... |
wire hi_byte; /* replicate data byte */
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wire hi_byte; /* replicate data byte */
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wire ld_m_aa, ld_m_ff, ld_m_bb, ld_m_cc; /* register loads */
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wire ld_m_aa, ld_m_ff, ld_m_bb, ld_m_cc; /* register loads */
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wire ld_m_dd, ld_m_ee, ld_m_hh, ld_m_ll;
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wire ld_m_dd, ld_m_ee, ld_m_hh, ld_m_ll;
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wire ld_a_aa, ld_a_ff, ld_a_bb, ld_a_cc;
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wire ld_a_aa, ld_a_ff, ld_a_bb, ld_a_cc;
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wire ld_a_dd, ld_a_ee, ld_a_hh, ld_a_ll;
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wire ld_a_dd, ld_a_ee, ld_a_hh, ld_a_ll;
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wire ld_sp, ld_ix, ld_iy;
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wire ld_sp;
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wire ld_ixh, ld_ixl, ld_iyh, ld_iyl;
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wire ld_ii, ld_rr, ld_tmp;
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wire ld_ii, ld_rr, ld_tmp;
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wire ld_dout_io, ld_dout_mem; /* load data out */
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wire ld_dout_io, ld_dout_mem; /* load data out */
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wire ld_flag; /* load flags */
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wire ld_flag; /* load flags */
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wire ld_regf; /* load register file */
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wire ld_regf; /* load register file */
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wire ld_tflg; /* load temp flag */
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wire ld_tflg; /* load temp flag */
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| Line 303... |
Line 305... |
assign ld_a_dd = ld_regf && wr_addr[`WR_DD] && alt_bnk_reg;
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assign ld_a_dd = ld_regf && wr_addr[`WR_DD] && alt_bnk_reg;
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assign ld_a_ee = ld_regf && wr_addr[`WR_EE] && alt_bnk_reg;
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assign ld_a_ee = ld_regf && wr_addr[`WR_EE] && alt_bnk_reg;
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assign ld_a_hh = ld_regf && wr_addr[`WR_HH] && alt_bnk_reg;
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assign ld_a_hh = ld_regf && wr_addr[`WR_HH] && alt_bnk_reg;
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assign ld_a_ll = ld_regf && wr_addr[`WR_LL] && alt_bnk_reg;
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assign ld_a_ll = ld_regf && wr_addr[`WR_LL] && alt_bnk_reg;
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assign ld_sp = ld_regf && wr_addr[`WR_SP];
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assign ld_sp = ld_regf && wr_addr[`WR_SP];
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assign ld_ix = ld_regf && wr_addr[`WR_IX];
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assign ld_ixh = ld_regf && wr_addr[`WR_IXH];
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assign ld_iy = ld_regf && wr_addr[`WR_IY];
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assign ld_ixl = ld_regf && wr_addr[`WR_IXL];
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assign ld_iyh = ld_regf && wr_addr[`WR_IYH];
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assign ld_iyl = ld_regf && wr_addr[`WR_IYL];
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assign ld_ii = ld_regf && wr_addr[`WR_II];
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assign ld_ii = ld_regf && wr_addr[`WR_II];
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assign ld_rr = ld_regf && wr_addr[`WR_RR];
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assign ld_rr = ld_regf && wr_addr[`WR_RR];
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assign ld_tmp = ld_regf && wr_addr[`WR_TMP];
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assign ld_tmp = ld_regf && wr_addr[`WR_TMP];
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|
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assign af_reg_out = (alt_af_reg) ? {a_aa_reg, a_ff_reg} : {m_aa_reg, m_ff_reg};
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assign af_reg_out = (alt_af_reg) ? {a_aa_reg, a_ff_reg} : {m_aa_reg, m_ff_reg};
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| Line 323... |
Line 327... |
assign zero_bit = af_reg_out[6];
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assign zero_bit = af_reg_out[6];
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assign hi_byte = (wr_addr[`WR_AA] && !wr_addr[`WR_FF]) ||
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assign hi_byte = (wr_addr[`WR_AA] && !wr_addr[`WR_FF]) ||
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(wr_addr[`WR_BB] && !wr_addr[`WR_CC]) ||
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(wr_addr[`WR_BB] && !wr_addr[`WR_CC]) ||
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(wr_addr[`WR_DD] && !wr_addr[`WR_EE]) ||
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(wr_addr[`WR_DD] && !wr_addr[`WR_EE]) ||
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(wr_addr[`WR_HH] && !wr_addr[`WR_LL]) ||
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(wr_addr[`WR_HH] && !wr_addr[`WR_LL]) ||
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(wr_addr[`WR_IXH]&& !wr_addr[`WR_IXL]) ||
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(wr_addr[`WR_IYH]&& !wr_addr[`WR_IYL]) ||
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wr_addr[`WR_II] || wr_addr[`WR_RR];
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wr_addr[`WR_II] || wr_addr[`WR_RR];
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/* cpu registers */
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/* cpu registers */
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| Line 368... |
Line 374... |
if (ld_a_cc) a_cc_reg <= data_bus[7:0];
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if (ld_a_cc) a_cc_reg <= data_bus[7:0];
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if (ld_a_dd) a_dd_reg <= de_reg_in[15:8];
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if (ld_a_dd) a_dd_reg <= de_reg_in[15:8];
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if (ld_a_ee) a_ee_reg <= de_reg_in[7:0];
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if (ld_a_ee) a_ee_reg <= de_reg_in[7:0];
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if (ld_a_hh) a_hh_reg <= data_bus[15:8];
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if (ld_a_hh) a_hh_reg <= data_bus[15:8];
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if (ld_a_ll) a_ll_reg <= data_bus[7:0];
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if (ld_a_ll) a_ll_reg <= data_bus[7:0];
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if (ld_ix) ix_reg <= data_bus;
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if (ld_ixh) ix_reg[15:8] <= data_bus[15:8];
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if (ld_iy) iy_reg <= data_bus;
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if (ld_ixl) ix_reg[7:0] <= data_bus[7:0];
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if (ld_iyh) iy_reg[15:8] <= data_bus[15:8];
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if (ld_iyl) iy_reg[7:0] <= data_bus[7:0];
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end
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end
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end
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end
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|
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always @ (posedge clkc or negedge resetb) begin
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always @ (posedge clkc or negedge resetb) begin
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if (!resetb) begin
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if (!resetb) begin
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| Line 384... |
Line 392... |
tmp_reg <= 16'h0000;
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tmp_reg <= 16'h0000;
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end
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end
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else begin
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else begin
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if (ld_ii) ii_reg <= data_bus[15:8];
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if (ld_ii) ii_reg <= data_bus[15:8];
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if (ld_pc) pc_reg <= data_bus;
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if (ld_pc) pc_reg <= data_bus;
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if (ld_rr) rr_reg <= data_bus[15:8];
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if (ld_rr)
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rr_reg <= data_bus[15:8];
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`ifdef RREG_EMU
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else
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rr_reg[6:0] <= rr_reg[6:0] + {6'h0, rreg_en && !dmar_reg && !wait_st};
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`endif
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if (ld_sp) sp_reg <= data_bus;
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if (ld_sp) sp_reg <= data_bus;
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if (ld_tmp) tmp_reg <= (ivec_rd) ? {ii_reg, data_in} : data_bus;
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if (ld_tmp) tmp_reg <= (ivec_rd) ? {ii_reg, data_in} : data_bus;
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end
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end
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end
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end
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