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/*******************************************************************************************/
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/*******************************************************************************************/
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/** **/
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/** **/
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/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
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/** **/
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/** **/
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/** data path module Rev 0.0 08/22/2010 **/
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/** data path module Rev 0.0 05/13/2012 **/
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/** **/
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/** **/
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/*******************************************************************************************/
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/*******************************************************************************************/
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module datapath (addr_reg_in, carry_bit, dmar_reg, dout_io_reg, dout_mem_reg, inst_reg,
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module datapath (addr_reg_in, carry_bit, dmar_reg, dout_io_reg, dout_mem_reg, inst_reg,
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intr_reg, page_reg, par_bit, sign_bit, tflg_reg, vector_int, xhlt_reg,
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intr_reg, page_reg, par_bit, sign_bit, tflg_reg, vector_int, xhlt_reg,
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zero_bit, add_sel, alua_sel, alub_sel, aluop_sel, clearb, clkc, cflg_en,
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zero_bit, add_sel, alua_sel, alub_sel, aluop_sel, clearb, clkc, cflg_en,
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wire [7:0] rst_addr; /* restart address */
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wire [7:0] rst_addr; /* restart address */
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wire [7:0] shft_out; /* shift result */
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wire [7:0] shft_out; /* shift result */
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wire [15:8] bsign_ext; /* address alu b sign extend */
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wire [15:8] bsign_ext; /* address alu b sign extend */
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wire [15:0] adda_in, addb_in; /* address alu inputs */
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wire [15:0] adda_in, addb_in; /* address alu inputs */
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wire [15:0] adder_out; /* math result */
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wire [15:0] adder_out; /* math result */
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wire [15:0] addr_alu, addr_hl, addr_pc, addr_sp; /* address mux terms */
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wire [15:0] addr_alu8, addr_alu, addr_hl, addr_pc, addr_sp; /* address mux terms */
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wire [15:0] addr_reg_in; /* address register input */
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wire [15:0] addr_reg_in; /* address register input */
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wire [15:0] alua_in, alub_in; /* alu inputs */
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wire [15:0] alua_in, alub_in; /* alu inputs */
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wire [15:0] data_bus; /* alu output */
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wire [15:0] data_bus; /* alu output */
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wire [15:0] de_reg_in; /* register inputs */
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wire [15:0] de_reg_in; /* register inputs */
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wire [15:0] af_reg_out, bc_reg_out; /* register outputs */
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wire [15:0] af_reg_out, bc_reg_out; /* register outputs */
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/*****************************************************************************************/
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/*****************************************************************************************/
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aluamux AMUX ( .adda_in(adda_in), .alua_in(alua_in), .alua_reg(alua_reg),
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aluamux AMUX ( .adda_in(adda_in), .alua_in(alua_in), .alua_reg(alua_reg),
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.aa_reg_out(aa_reg_out), .bit_mask(bit_mask), .daa_out(daa_out),
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.aa_reg_out(aa_reg_out), .bit_mask(bit_mask), .daa_out(daa_out),
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.hl_reg_out(hl_reg_out), .ii_reg(ii_reg), .int_addr(int_addr),
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.hl_reg_out(hl_reg_out), .ii_reg(ii_reg), .int_addr(int_addr),
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.ix_reg(ix_reg), .iy_reg(iy_reg), .pc_reg(pc_reg), .rr_reg(rr_reg),
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.ix_reg(ix_reg), .iy_reg(iy_reg), .pc_reg(pc_reg), .rr_reg(rr_reg),
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.rst_addr(rst_addr) );
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.rst_addr(rst_addr), .tmp_reg(tmp_reg) );
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alubmux BMUX ( .addb_in(addb_in), .alub_in(alub_in), .alub_reg(alub_reg),
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alubmux BMUX ( .addb_in(addb_in), .alub_in(alub_in), .alub_reg(alub_reg),
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.af_reg_out(af_reg_out), .bc_reg_out(bc_reg_out), .de_reg_out(de_reg_out),
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.af_reg_out(af_reg_out), .bc_reg_out(bc_reg_out), .de_reg_out(de_reg_out),
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.din0_reg(din0_reg), .din1_reg(din1_reg), .hl_reg_out(hl_reg_out),
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.din0_reg(din0_reg), .din1_reg(din1_reg), .hl_reg_out(hl_reg_out),
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.ix_reg(ix_reg), .iy_reg(iy_reg), .pc_reg(pc_reg), .sp_reg(sp_reg),
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.ix_reg(ix_reg), .iy_reg(iy_reg), .pc_reg(pc_reg), .sp_reg(sp_reg),
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.aluop_reg(aluop_reg[`AOP_IDX:0]), .carry_bit(carry_bit),
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.aluop_reg(aluop_reg[`AOP_IDX:0]), .carry_bit(carry_bit),
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.carry_daa(carry_daa), .daa_op(daa_op), .word_op(word_op) );
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.carry_daa(carry_daa), .daa_op(daa_op), .word_op(word_op) );
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alu_shft ALUSHFT ( .shft_c(shft_c), .shft_out(shft_out), .alub_in(alub_in[7:0]),
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alu_shft ALUSHFT ( .shft_c(shft_c), .shft_out(shft_out), .alub_in(alub_in[7:0]),
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.aluop_reg(aluop_reg[`AOP_IDX:0]), .carry_bit(carry_bit) );
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.aluop_reg(aluop_reg[`AOP_IDX:0]), .carry_bit(carry_bit) );
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wire [15:0] mult_out = alub_in[15:8] * alub_in[7:0];
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aluout ALUOUT ( .cry_nxt(cry_nxt), .data_bus(data_bus), .hcar_nxt(hcar_nxt),
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aluout ALUOUT ( .cry_nxt(cry_nxt), .data_bus(data_bus), .hcar_nxt(hcar_nxt),
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.one_nxt(one_nxt), .par_nxt(par_nxt), .sign_nxt(sign_nxt),
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.one_nxt(one_nxt), .par_nxt(par_nxt), .sign_nxt(sign_nxt),
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.zero_nxt(zero_nxt), .adder_c(adder_c), .adder_hc(adder_hc),
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.zero_nxt(zero_nxt), .adder_c(adder_c), .adder_hc(adder_hc),
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.adder_out(adder_out), .hi_byte(hi_byte), .logic_c(logic_c),
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.adder_out(adder_out), .hi_byte(hi_byte), .logic_c(logic_c),
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.logic_hc(logic_hc), .logic_out(logic_out), .shft_c(shft_c),
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.logic_hc(logic_hc), .logic_out(logic_out), .shft_c(shft_c),
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.shft_out(shft_out), .unit_sel(aluop_reg[7:6]), .word_op(word_op) );
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.shft_out(shft_out), .mult_out(mult_out), .unit_sel(aluop_reg[7:6]), .word_op(word_op) );
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/* flag generation */
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/* flag generation */
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/* */
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/* */
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addb_in[7], addb_in[7], addb_in[7], addb_in[7]};
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addb_in[7], addb_in[7], addb_in[7], addb_in[7]};
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always @ (aluop_reg or adda_in or addb_in or bsign_ext) begin
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always @ (aluop_reg or adda_in or addb_in or bsign_ext) begin
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case (aluop_reg)
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case (aluop_reg)
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`ALUOP_ADS: adda_out = adda_in + {bsign_ext[15:8], addb_in[7:0]};
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`ALUOP_ADS: adda_out = adda_in + {bsign_ext[15:8], addb_in[7:0]};
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`ALUOP_BADD,
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`ALUOP_ADD: adda_out = adda_in + addb_in;
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`ALUOP_ADD: adda_out = adda_in + addb_in;
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`ALUOP_APAS: adda_out = adda_in;
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`ALUOP_APAS: adda_out = adda_in;
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default: adda_out = addb_in;
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default: adda_out = addb_in;
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endcase
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endcase
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end
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end
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assign addr_alu8 = (addsel_reg[`AD_ALU8]) ? {8'h00, adda_out[7:0]} : 16'h0000;
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assign addr_alu = (addsel_reg[`AD_ALU]) ? adda_out : 16'h0000;
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assign addr_alu = (addsel_reg[`AD_ALU]) ? adda_out : 16'h0000;
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assign addr_hl = (addsel_reg[`AD_HL]) ? hl_reg_out : 16'h0000;
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assign addr_hl = (addsel_reg[`AD_HL]) ? hl_reg_out : 16'h0000;
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assign addr_pc = (addsel_reg[`AD_PC]) ? pc_reg : 16'h0000;
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assign addr_pc = (addsel_reg[`AD_PC]) ? pc_reg : 16'h0000;
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assign addr_sp = (addsel_reg[`AD_SP]) ? sp_reg : 16'h0000;
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assign addr_sp = (addsel_reg[`AD_SP]) ? sp_reg : 16'h0000;
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assign addr_reg_in = addr_alu | addr_hl | addr_pc | addr_sp;
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assign addr_reg_in = addr_alu8 | addr_alu | addr_hl | addr_pc | addr_sp;
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endmodule
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endmodule
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