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/*******************************************************************************************/
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/*******************************************************************************************/
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/** **/
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/** **/
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/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
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/** **/
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/** **/
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/** define file to make the code more readable Rev 0.0 07/29/2011 **/
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/** define file to make the code more readable Rev 0.0 06/13/2012 **/
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/** **/
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/** **/
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/*******************************************************************************************/
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/*******************************************************************************************/
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/* address bus select: add_sel */
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/* address bus select: add_sel */
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/* */
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/* */
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/*****************************************************************************************/
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/*****************************************************************************************/
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`define ADCTL_IDX 3
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`define ADCTL_IDX 4
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`define ADD_RSTVAL 4'b0000 //Pipeline register reset value
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`define ADD_RSTVAL 5'b00000 //Pipeline register reset value
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`define ADD_PC 4'b0001 //Select address register from PC
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`define ADD_PC 5'b00001 //Select address register from PC
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`define ADD_HL 4'b0010 //Select address register from HL
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`define ADD_HL 5'b00010 //Select address register from HL
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`define ADD_SP 4'b0100 //Select address register from SP
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`define ADD_SP 5'b00100 //Select address register from SP
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`define ADD_ALU 4'b1000 //Select address register from ALU
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`define ADD_ALU 5'b01000 //Select address register from ALU
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`define ADD_ALU8 5'b10000 //Select address register from {8'h0, ALU[7:0]}
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`define AD_PC 0 //Address from PC
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`define AD_PC 0 //Address from PC
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`define AD_HL 1 //Address from HL
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`define AD_HL 1 //Address from HL
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`define AD_SP 2 //Address from SP
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`define AD_SP 2 //Address from SP
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`define AD_ALU 3 //Address from ALU
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`define AD_ALU 3 //Address from ALU
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`define AD_ALU8 4 //Address from {8'h0, ALU[7:0]}
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/* transaction type select: tran_sel */
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/* transaction type select: tran_sel */
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/* */
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/* */
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/* ALU input A control: alua_sel */
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/* ALU input A control: alua_sel */
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/* */
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/* */
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/*****************************************************************************************/
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/*****************************************************************************************/
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`define ALUA_IDX 13
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`define ALUA_IDX 14
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`define ALUA_RSTVAL 14'h0000 //Reset value for pipeline controls
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`define ALUA_RSTVAL 15'h0000 //Reset value for pipeline controls
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`define ALUA_ZER 14'h0000 //Select 16'h0000 (default)
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`define ALUA_ZER 15'h0000 //Select 16'h0000 (default)
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`define ALUA_ONE 14'h0001 //Select 16'h0001
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`define ALUA_ONE 15'h0001 //Select 16'h0001
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`define ALUA_M1 14'h0002 //Select 16'hFFFF
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`define ALUA_M1 15'h0002 //Select 16'hFFFF
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`define ALUA_M2 14'h0004 //Select 16'hFFFE
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`define ALUA_M2 15'h0004 //Select 16'hFFFE
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`define ALUA_HL 14'h0008 //Select HL register
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`define ALUA_HL 15'h0008 //Select HL register
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`define ALUA_IX 14'h0010 //Select IX register
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`define ALUA_IX 15'h0010 //Select IX register
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`define ALUA_IY 14'h0020 //Select IY register
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`define ALUA_IY 15'h0020 //Select IY register
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`define ALUA_PC 14'h0040 //Select PC register
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`define ALUA_PC 15'h0040 //Select PC register
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`define ALUA_AA 14'h0080 //Select A register
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`define ALUA_AA 15'h0080 //Select A register
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`define ALUA_BIT 14'h0100 //Select bit select constant
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`define ALUA_BIT 15'h0100 //Select bit select constant
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`define ALUA_DAA 14'h0200 //Select decimal adjust constant
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`define ALUA_DAA 15'h0200 //Select decimal adjust constant
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`define ALUA_II 14'h0400 //Select I register
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`define ALUA_II 15'h0400 //Select I register
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`define ALUA_RR 14'h0800 //Select R register
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`define ALUA_RR 15'h0800 //Select R register
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`define ALUA_INT 14'h1000 //Select interrupt address
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`define ALUA_INT 15'h1000 //Select interrupt address
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`define ALUA_RST 14'h2000 //Select restart address
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`define ALUA_TMP 15'h2000 //Select TMP register
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`define ALUA_RST 15'h4000 //Select restart address
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`define AA_ONE 0 //alua one
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`define AA_ONE 0 //alua one
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`define AA_M1 1 //alua -1
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`define AA_M1 1 //alua -1
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`define AA_M2 2 //alua -2
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`define AA_M2 2 //alua -2
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`define AA_HL 3 //alua hl
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`define AA_HL 3 //alua hl
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`define AA_BIT 8 //alua bit
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`define AA_BIT 8 //alua bit
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`define AA_DAA 9 //alua daa
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`define AA_DAA 9 //alua daa
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`define AA_II 10 //alua ii
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`define AA_II 10 //alua ii
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`define AA_RR 11 //alua rr
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`define AA_RR 11 //alua rr
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`define AA_INT 12 //alua interrupt
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`define AA_INT 12 //alua interrupt
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`define AA_RST 13 //alua restart
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`define AA_TMP 13 //alua tmp
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`define AA_RST 14 //alua restart
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/* ALU input B control: alub_sel */
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/* ALU input B control: alub_sel */
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/* */
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/* */
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`define ALUOP_SLA 8'b10010000 //ALU shft: shift left arithmetic
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`define ALUOP_SLA 8'b10010000 //ALU shft: shift left arithmetic
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`define ALUOP_SLL 8'b10011000 //ALU shft: shift left logical (x = (x << 1) | 1)
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`define ALUOP_SLL 8'b10011000 //ALU shft: shift left logical (x = (x << 1) | 1)
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`define ALUOP_SRL 8'b10100000 //ALU shft: shift right logical
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`define ALUOP_SRL 8'b10100000 //ALU shft: shift right logical
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`define ALUOP_SRA 8'b10101000 //ALU shft: shift right arithmetic
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`define ALUOP_SRA 8'b10101000 //ALU shft: shift right arithmetic
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`define ALUOP_MLT 8'b11000000 //ALU mult: 8 bit multiplication
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/* ALU operation control: 6 encoded */
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/* ALU operation control: 6 encoded */
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/* */
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/* */
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/*****************************************************************************************/
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/*****************************************************************************************/
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`define AOP_SLA 6'b010000 //ALU shft: shift left arithmetic
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`define AOP_SLA 6'b010000 //ALU shft: shift left arithmetic
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`define AOP_SLL 6'b011000 //ALU shft: shift left logical
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`define AOP_SLL 6'b011000 //ALU shft: shift left logical
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`define AOP_SRL 6'b100000 //ALU shft: shift right logical
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`define AOP_SRL 6'b100000 //ALU shft: shift right logical
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`define AOP_SRA 6'b101000 //ALU shft: shift right arithmetic
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`define AOP_SRA 6'b101000 //ALU shft: shift right arithmetic
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`define AOP_MLT 6'b000000 //ALU mult: 8 bit multiplication
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/*****************************************************************************************/
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/*****************************************************************************************/
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/* */
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/* */
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/* machine state - pseudo-one-hot */
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/* machine state - pseudo-one-hot */
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/* */
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/* */
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/*****************************************************************************************/
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/*****************************************************************************************/
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