| Line 73... |
Line 73... |
wire par_bit; /* parity flag */
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wire par_bit; /* parity flag */
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wire rd_brst; /* burst read */
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wire rd_brst; /* burst read */
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wire rd_frst; /* first clock of read */
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wire rd_frst; /* first clock of read */
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wire rd_nxt; /* read trans next */
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wire rd_nxt; /* read trans next */
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wire reti_nxt, reti_tran; /* reti transaction */
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wire reti_nxt, reti_tran; /* reti transaction */
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wire rreg_en; /* update refresh register */
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wire sflg_en; /* sign flag control */
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wire sflg_en; /* sign flag control */
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wire sign_bit; /* sign flag */
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wire sign_bit; /* sign flag */
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wire tflg_reg; /* temporary flag */
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wire tflg_reg; /* temporary flag */
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wire t1; /* first clock of transaction */
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wire t1; /* first clock of transaction */
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wire vector_int; /* int vector enable */
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wire vector_int; /* int vector enable */
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| Line 156... |
Line 157... |
.ief_ctl(ief_ctl), .if_frst(if_frst), .inta_frst(inta_frst),
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.ief_ctl(ief_ctl), .if_frst(if_frst), .inta_frst(inta_frst),
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.imd_ctl(imd_ctl), .ld_dmaa(ld_dmaa), .ld_inst(ld_inst),
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.imd_ctl(imd_ctl), .ld_dmaa(ld_dmaa), .ld_inst(ld_inst),
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.ld_inta(ld_inta), .ld_page(ld_page), .ld_wait(ld_wait),
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.ld_inta(ld_inta), .ld_page(ld_page), .ld_wait(ld_wait),
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.nflg_ctl(nflg_ctl), .output_inh(output_inh), .page_sel(page_sel),
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.nflg_ctl(nflg_ctl), .output_inh(output_inh), .page_sel(page_sel),
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.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .rd_frst(rd_frst),
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.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .rd_frst(rd_frst),
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.rd_nxt(rd_nxt), .reti_nxt(reti_nxt), .sflg_en(sflg_en),
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.rd_nxt(rd_nxt), .reti_nxt(reti_nxt), .rreg_en(rreg_en), .sflg_en(sflg_en),
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.state_nxt(state_nxt), .tflg_ctl(tflg_ctl), .tran_sel(tran_sel),
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.state_nxt(state_nxt), .tflg_ctl(tflg_ctl), .tran_sel(tran_sel),
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.wr_addr(wr_addr), .wr_frst(wr_frst), .zflg_en(zflg_en),
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.wr_addr(wr_addr), .wr_frst(wr_frst), .zflg_en(zflg_en),
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.carry_bit(carry_bit), .dmar_reg(dmar_reg), .inst_reg(inst_reg),
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.carry_bit(carry_bit), .dmar_reg(dmar_reg), .inst_reg(inst_reg),
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.intr_reg(intr_reg), .page_reg(page_reg), .par_bit(par_bit),
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.intr_reg(intr_reg), .page_reg(page_reg), .par_bit(par_bit),
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.sign_bit(sign_bit), .state_reg(state_reg), .tflg_reg(tflg_reg),
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.sign_bit(sign_bit), .state_reg(state_reg), .tflg_reg(tflg_reg),
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| Line 182... |
Line 183... |
.ex_af_pls(ex_af_pls), .ex_bank_pls(ex_bank_pls),
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.ex_af_pls(ex_af_pls), .ex_bank_pls(ex_bank_pls),
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.ex_dehl_inst(ex_dehl_inst), .hflg_ctl(hflg_ctl), .ief_ctl(ief_ctl),
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.ex_dehl_inst(ex_dehl_inst), .hflg_ctl(hflg_ctl), .ief_ctl(ief_ctl),
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.imd_ctl(imd_ctl), .int_req(int_req), .ivec_rd(ivec_rd),
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.imd_ctl(imd_ctl), .int_req(int_req), .ivec_rd(ivec_rd),
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.ld_ctrl(ld_ctrl), .ld_inst(ld_inst), .ld_page(ld_page),
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.ld_ctrl(ld_ctrl), .ld_inst(ld_inst), .ld_page(ld_page),
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.nflg_ctl(nflg_ctl), .nmi_req(nmi_req), .page_sel(page_sel),
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.nflg_ctl(nflg_ctl), .nmi_req(nmi_req), .page_sel(page_sel),
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.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .resetb(resetb),
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.pc_sel(pc_sel), .pflg_ctl(pflg_ctl), .resetb(resetb), .rreg_en(rreg_en),
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.sflg_en(sflg_en), .tflg_ctl(tflg_ctl), .wait_st(wait_st),
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.sflg_en(sflg_en), .tflg_ctl(tflg_ctl), .wait_st(wait_st),
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.wr_addr(wr_addr), .zflg_en(zflg_en) );
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.wr_addr(wr_addr), .zflg_en(zflg_en) );
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endmodule
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endmodule
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