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[/] [yac/] [trunk/] [README.txt] - Diff between revs 4 and 6
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Status
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Status
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- C-model implementation is done
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- C-model implementation is done
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- RTL model implementation is done
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- RTL model implementation is done
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- RTL model is verified against C-model
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- RTL model is verified against C-model
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- Wishbone-bus wrapper is added
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- included into a small SoC, tested on a spartan-3 FPGA
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Next-Steps
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Next-Steps
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- Prove of FPGA feasibility
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- Circuit optimizations
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- Circuit optimizations
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- Numerical optimizations
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- Numerical optimizations
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- Further testing within an SOC
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