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[/] [yac/] [trunk/] [README.txt] - Diff between revs 4 and 6

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Status
Status
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- C-model implementation is done
- C-model implementation is done
- RTL model implementation is done
- RTL model implementation is done
- RTL model is verified against C-model
- RTL model is verified against C-model
 
- Wishbone-bus wrapper is added
 
- included into a small SoC, tested on a spartan-3 FPGA
 
 
 
 
 
 
 
 
Next-Steps
Next-Steps
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- Prove of FPGA feasibility
 
- Circuit optimizations
- Circuit optimizations
- Numerical optimizations
- Numerical optimizations
 
- Further testing within an SOC
 
 
 
 
 
 
 
 
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