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[/] [yac/] [trunk/] [rtl/] [vhdl/] [cordic_iterative_tb.vhd] - Diff between revs 4 and 7

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Rev 4 Rev 7
Line 78... Line 78...
   constant clk_T       : time := 5 ns;
   constant clk_T       : time := 5 ns;
   signal clk           : std_logic;
   signal clk           : std_logic;
   signal rst           : std_logic;
   signal rst           : std_logic;
   signal nrst          : std_logic;
   signal nrst          : std_logic;
 
 
   constant XY_WIDTH    : natural := 25;
   constant XY_WIDTH    : natural := 8;
   constant A_WIDTH     : natural := 25;
   constant A_WIDTH     : natural := 8;
   constant GUARD_BITS  : natural :=  2;
   constant GUARD_BITS  : natural :=  2;
   constant RM_GAIN     : natural :=  5;
   constant RM_GAIN     : natural := 3;
   component cordic_iterative_int is
   component cordic_iterative_int is
   generic(
   generic(
      XY_WIDTH    : natural := 12;
      XY_WIDTH    : natural := 12;
      A_WIDTH     : natural := 12;
      A_WIDTH     : natural := 12;
      GUARD_BITS  : natural :=  2;
      GUARD_BITS  : natural :=  2;
Line 115... Line 115...
   signal x_o       : std_logic_vector( XY_WIDTH+GUARD_BITS-1  downto 0 );
   signal x_o       : std_logic_vector( XY_WIDTH+GUARD_BITS-1  downto 0 );
   signal y_o       : std_logic_vector( XY_WIDTH+GUARD_BITS-1  downto 0 );
   signal y_o       : std_logic_vector( XY_WIDTH+GUARD_BITS-1  downto 0 );
   signal a_o       : std_logic_vector( A_WIDTH+2-1 downto 0 );
   signal a_o       : std_logic_vector( A_WIDTH+2-1 downto 0 );
 
 
 
 
 
 
begin
begin
 
 
 
 
   -- --
   -- --
   -- clock and reset 
   -- clock and reset 
Line 215... Line 214...
 
 
    wait until clk'event and clk='1';
    wait until clk'event and clk='1';
 
 
    while ( not endfile( test_pattern_file ) )loop
    while ( not endfile( test_pattern_file ) )loop
 
 
 
 
        wait until en='1';
        wait until en='1';
        wait for clk_T;
        wait for clk_T;
 
 
 
 
        -- read line and extract values
        -- read line and extract values
Line 252... Line 250...
           a_ex /= a_o then
           a_ex /= a_o then
           assert x_ex = x_o report
           assert x_ex = x_o report
<<<<<<< HEAD
<<<<<<< HEAD
<<<<<<< HEAD
<<<<<<< HEAD
                 integer'image( stim_cnt ) & ": Serial Cordic Failed: expected x result:"
                 integer'image( stim_cnt ) & ": Serial Cordic Failed: expected x result:"
                 & integer'image( tmp_value(5) ) & ", but got:"
                 & integer'image( tmp_value(3) ) & ", but got:"
                 & integer'image( to_integer( signed( x_ex ) ) );
                 & integer'image( to_integer( signed( x_o ) ) );
           assert y_ex = y_o report
           assert y_ex = y_o report
                 integer'image( stim_cnt ) &   ": Serial Cordic Failed: expected y result:"
                 integer'image( stim_cnt ) &   ": Serial Cordic Failed: expected y result:"
                 & integer'image( tmp_value(6) ) & ", but got:"
                 & integer'image( tmp_value(4) ) & ", but got:"
                 & integer'image( to_integer( signed( y_ex ) ) );
                 & integer'image( to_integer( signed( y_o ) ) );
           assert a_ex = a_o report
           assert a_ex = a_o report
                 integer'image( stim_cnt ) &   ": Serial Cordic Failed: expected a result:"
                 integer'image( stim_cnt ) &   ": Serial Cordic Failed: expected a result:"
 
<<<<<<< HEAD
=======
=======
                   " Serial Cordic Failed: expected x result:"
                   " Serial Cordic Failed: expected x result:"
=======
=======
                 integer'image( stim_cnt ) & ": Serial Cordic Failed: expected x result:"
                 integer'image( stim_cnt ) & ": Serial Cordic Failed: expected x result:"
>>>>>>> Updated C and RTL model as well as the documentation
>>>>>>> Updated C and RTL model as well as the documentation
Line 280... Line 279...
=======
=======
                 integer'image( stim_cnt ) &   ": Serial Cordic Failed: expected a result:"
                 integer'image( stim_cnt ) &   ": Serial Cordic Failed: expected a result:"
>>>>>>> Updated C and RTL model as well as the documentation
>>>>>>> Updated C and RTL model as well as the documentation
                 & integer'image( tmp_value(7) ) & ", but got:"
                 & integer'image( tmp_value(7) ) & ", but got:"
                 & integer'image( to_integer( signed( a_ex ) ) );
                 & integer'image( to_integer( signed( a_ex ) ) );
 
=======
 
                 & integer'image( tmp_value(5) ) & ", but got:"
 
                 & integer'image( to_integer( signed( a_o ) ) );
 
>>>>>>> Removed some bugs regarding pre-rotation and negative numbers in the wb wrapper
            err_cnt := err_cnt + 1;
            err_cnt := err_cnt + 1;
         writeline( error_pattern_file, input_line_bak );
         writeline( error_pattern_file, input_line_bak );
 
 
        end if;
        end if;
 
 

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