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-------------------------------------------------------------------------------
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-- Yahamm IP core
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--
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-- This file is part of the Yahamm project
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-- http://www.opencores.org/cores/yahamm
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--
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-- Description
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-- A hamming encoder and decoder with single-error correcting and
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-- double-error detecting capability. The message length can be configured
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-- through a generic. Both the code generator matrix and the parity-check
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-- matrix are computed in the VHDL itself.
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--
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-- To Do:
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-- - write docs
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--
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-- Author:
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-- - Nicola De Simone, ndesimone@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2017 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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--- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library yahamm;
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use yahamm.matrix_pkg.all;
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use yahamm.yahamm_pkg.all;
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library std;
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use std.textio.all;
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-- There are two monitor counters:
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--
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-- cnt_errors_corrected: number of error correction performed.
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-- cnt_errors_detected: numbers of errors detected but not corrected.
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--
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-- The two never count together and they don't overflow. If CORRECT
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-- is false, no correction is performed cnt_errors_corrected never counts.
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-- If CORRECT is true and EXTRA_PARITY_BIT is true, cnt_errors_detected
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-- never counts because all errors (supposedly single-bit errors) are
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-- corrected.
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--
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-- ERROR_LEN: width of the cnt_errors_corrected and cnt_errors_detected counters.
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--
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-- dout_valid_o: dout data valid, it's the en input pipelined. It takes into
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-- account the total latency.
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--
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entity yahamm_dec is
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generic (
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MESSAGE_LENGTH : natural := 5;
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CORRECT : boolean := true;
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EXTRA_PARITY_BIT : natural range 0 to 1 := 1;
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ONE_PARITY_BIT : boolean := false;
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ERROR_LEN : natural := 16
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);
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port(
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clk_i, rst_i : in std_logic;
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cnt_clr_i : in std_logic := '0'; -- Clear monitor counters.
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en_i : in std_logic := '1'; -- Input enable.
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data_i : in std_logic_vector(MESSAGE_LENGTH - 1 downto 0); -- Input data.
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parity_i : in std_logic_vector(calc_nparity_bits(MESSAGE_LENGTH, ONE_PARITY_BIT) + EXTRA_PARITY_BIT - 1 downto 0); -- Parity bits.
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data_o : out std_logic_vector(MESSAGE_LENGTH - 1 downto 0); -- Out data.
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dout_valid_o : out std_logic; -- data_o valid.
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cnt_errors_corrected_o, cnt_errors_detected_o : out std_logic_vector(ERROR_LEN - 1 downto 0);
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log_wrong_bit_pos_data_o : out std_logic_vector(MESSAGE_LENGTH - 1 downto 0);
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log_wrong_bit_pos_parity_o : out std_logic_vector(calc_nparity_bits(MESSAGE_LENGTH, ONE_PARITY_BIT) + EXTRA_PARITY_BIT - 1 downto 0)
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);
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end yahamm_dec;
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architecture std of yahamm_dec is
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constant NPARITY_BITS : natural := calc_nparity_bits(MESSAGE_LENGTH, ONE_PARITY_BIT);
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constant BLOCK_LENGTH : natural := calc_block_length(MESSAGE_LENGTH, ONE_PARITY_BIT);
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constant H : matrix_t(0 to NPARITY_BITS + EXTRA_PARITY_BIT - 1,
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0 to BLOCK_LENGTH + EXTRA_PARITY_BIT - 1) :=
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get_parity_check_matrix(MESSAGE_LENGTH, EXTRA_PARITY_BIT, ONE_PARITY_BIT);
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signal data_i_padded : bit_vector(BLOCK_LENGTH - NPARITY_BITS - 1 downto 0);
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signal code_sys, code_nonsys, code_nonsys_q : bit_vector(BLOCK_LENGTH + EXTRA_PARITY_BIT - 1 downto 0);
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signal syndrome : bit_vector(NPARITY_BITS + EXTRA_PARITY_BIT - 1 downto 0);
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signal wrong_bit : integer range 0 to code_sys'length;
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constant SWAPM : matrix_t(0 to BLOCK_LENGTH + EXTRA_PARITY_BIT - 1,
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0 to BLOCK_LENGTH + EXTRA_PARITY_BIT - 1) :=
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get_form_swap_matrix(MESSAGE_LENGTH, EXTRA_PARITY_BIT, ONE_PARITY_BIT);
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signal correction_en : boolean;
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signal cnt_errors_corrected_o_int, cnt_errors_detected_o_int : unsigned(ERROR_LEN - 1 downto 0);
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signal log_wrong_bit_pos_data_o_sys, log_wrong_bit_pos_data_o_nonsys : bit_vector(BLOCK_LENGTH + EXTRA_PARITY_BIT - 1 downto 0);
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signal dout_valid_o_p0 : std_logic;
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begin
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check_parameters(BLOCK_LENGTH, NPARITY_BITS, MESSAGE_LENGTH, EXTRA_PARITY_BIT, ONE_PARITY_BIT, CORRECT);
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cnt_errors_corrected_o <= std_logic_vector(cnt_errors_corrected_o_int);
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cnt_errors_detected_o <= std_logic_vector(cnt_errors_detected_o_int);
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-- Pad data_i with zeros on the left, so that data_i_padded'length = BLOCK_LENGTH.
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-- This allow the user to reduce data_i width.
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data_i_padded(MESSAGE_LENGTH - 1 downto 0) <= to_bitvector(data_i);
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gen_padding: if BLOCK_LENGTH - NPARITY_BITS > MESSAGE_LENGTH generate
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data_i_padded(BLOCK_LENGTH - NPARITY_BITS - 1 downto MESSAGE_LENGTH) <= (others => '0');
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end generate gen_padding;
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-- Wire data and parity inputs in the systematic code code_sys (data
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-- on LSB, parity on MSB).
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code_sys <= to_bitvector(parity_i) & data_i_padded;
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-- Get the non-systematic code code_nonsys by swapping the
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-- systematic code code_sys. The non-systematic code is needed to
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-- obtain an immediately meaningful syndrome. This is timing-safe:
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-- no logic here, it's purely wiring.
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code_nonsys <= xor_multiply_vec(SWAPM, code_sys);
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-- Output log_wrong_bit_pos_log, uses log_wrong_bit_pos_log_nonsys is padded
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-- as data_i_padded
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log_wrong_bit_pos_data_o_sys <= xor_multiply_vec(SWAPM, log_wrong_bit_pos_data_o_nonsys);
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log_wrong_bit_pos_data_o <= To_StdLogicVector(log_wrong_bit_pos_data_o_sys(MESSAGE_LENGTH-1 downto 0));
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log_wrong_bit_pos_parity_o <= To_StdLogicVector(log_wrong_bit_pos_data_o_sys(BLOCK_LENGTH + EXTRA_PARITY_BIT - 1 downto BLOCK_LENGTH - NPARITY_BITS));
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-- purpose: Compute error syndrome from the non-systematic code
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-- (input) and the non-systemacic parity check matrix H. Also delay
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-- code_nonsys to have code_nonsys_q synchronous with syndrome. And start
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-- pipelining en input.
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-- type : sequential
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-- inputs : clk_i, rst_i, code_nonsys
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-- outputs: syndrome
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syndrome_proc: process (clk_i, rst_i) is
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begin -- process syndrome_proc
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if rst_i = '1' then -- asynchronous reset (active high)
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syndrome <= (others => '0');
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code_nonsys_q <= (others => '0');
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dout_valid_o_p0 <= '0';
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elsif rising_edge(clk_i) then -- rising clock edge
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syndrome <= xor_multiply_vec(H, code_nonsys);
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code_nonsys_q <= code_nonsys;
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dout_valid_o_p0 <= en_i;
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end if;
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end process syndrome_proc;
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-- purpose: Enable error correction (signal correction_en) for a single bit
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-- error. Dependent from the generic parameters. If correction is enabled
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-- wrong_bit signal is assigned the position of the wrong bit.
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-- type : combinational
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-- inputs : syndrome
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-- outputs: correction_enabled
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correction_enable_proc: process (syndrome) is
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begin -- process correction_enable_proc
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wrong_bit <= 0;
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case CORRECT is
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when false =>
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-- Entity does not implement correction.
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correction_en <= false;
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when true =>
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-- Entity implements correction.
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case EXTRA_PARITY_BIT is
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when 0 =>
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-- SEC case (see table). Always correct.
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correction_en <= true;
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-- The wrong bit is the syndrome itself.
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wrong_bit <= to_integer(unsigned(To_StdULogicVector(syndrome)));
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when 1 =>
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-- SECDED case (see table). The error, if any, is a single error to be
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-- corrected if the extra parity bit in the syndrome is '1'.
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if syndrome(syndrome'high) = '0' then
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-- Double error: don't correct.
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correction_en <= false;
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else
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-- Single error: correct.
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correction_en <= true;
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-- The wrong bit is not just the syndrome, because the
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-- syndrome has the extra parity bit as MSB bit.
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if or_reduce(syndrome(syndrome'high-1 downto 0)) = '0' then
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-- No other error. So the extra parity bit itself is
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-- wrong, that in this implementation is the MSB of
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-- the non-systematic code word.
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wrong_bit <= code_nonsys_q'length;
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else
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-- Extra parity bit '1', ignore it for wrong_bit position.
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wrong_bit <= to_integer(unsigned(To_StdULogicVector(syndrome(NPARITY_BITS-1 downto 0))));
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end if;
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end if;
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end case;
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end case;
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end process correction_enable_proc;
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-- purpose: Decode the non systematic code code_nonsys_q and drive
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-- output data_o. Single error correction is performed, depending on
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-- the configuration.
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-- type : sequential
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-- inputs : clk_i, rst_i, code_nonsys_q, syndrome
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-- outputs: data_o
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decode_proc: process (clk_i, rst_i) is
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variable iserror : boolean; -- parity error condition
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variable code_sys_dec, code_nonsys_dec : bit_vector(code_sys'range);
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begin -- process decode_proc
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if rst_i = '1' then -- asynchronous reset (active high)
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data_o <= (others => '0');
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dout_valid_o <= '0';
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elsif rising_edge(clk_i) then -- rising clock edge
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if dout_valid_o_p0 = '0' then
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data_o <= (others => '0');
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dout_valid_o <= '0';
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else
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code_nonsys_dec := code_nonsys_q;
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iserror := or_reduce(syndrome) = '1';
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if correction_en and iserror then
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code_nonsys_dec(wrong_bit-1) := not code_nonsys_q(wrong_bit-1);
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end if;
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code_sys_dec := xor_multiply_vec(SWAPM, code_nonsys_dec);
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data_o <= To_StdLogicVector(code_sys_dec(MESSAGE_LENGTH - 1 downto 0));
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dout_valid_o <= '1';
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end if;
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end if;
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end process decode_proc;
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-- purpose: Monitor counters.
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-- type : sequential
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-- inputs : clk_i, rst_i, syndrome, correction_en
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-- outputs: cnt_errors_corrected_o_int, cnt_errors_detected_o_int, log_wrong_bit_pos_log
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cnt_proc: process (clk_i, rst_i) is
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variable iserror : boolean; -- parity error condition
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begin -- process cnt_proc
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if rst_i = '1' then -- asynchronous reset (active high)
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cnt_errors_detected_o_int <= (others => '0');
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cnt_errors_corrected_o_int <= (others => '0');
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elsif rising_edge(clk_i) then -- rising clock edge
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if cnt_clr_i = '1' then
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-- synchronous clear
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cnt_errors_detected_o_int <= (others => '0');
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cnt_errors_corrected_o_int <= (others => '0');
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else
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iserror := or_reduce(syndrome) = '1';
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if iserror then
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if correction_en then
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if and_reduce(to_bitvector(std_logic_vector(cnt_errors_corrected_o_int))) /= '1' then
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cnt_errors_corrected_o_int <= cnt_errors_corrected_o_int + 1;
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end if;
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else
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if and_reduce(to_bitvector(std_logic_vector(cnt_errors_detected_o_int))) /= '1' then
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cnt_errors_detected_o_int <= cnt_errors_detected_o_int + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process cnt_proc;
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-- purpose: Monitor counters.
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-- type : sequential
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-- inputs : clk_i, rst_i, syndrome, correction_en
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-- outputs: cnt_errors_corrected_o_int, cnt_errors_detected_o_int, log_wrong_bit_pos_log
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log_wrong_bit_gen: if CORRECT generate
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log_wrong_bit_proc: process (clk_i, rst_i) is
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variable iserror : boolean; -- parity error condition
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begin -- process cnt_proc
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if rst_i = '1' then
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log_wrong_bit_pos_data_o_nonsys <= (others => '0');
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elsif rising_edge(clk_i) then
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if cnt_clr_i = '1' then
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log_wrong_bit_pos_data_o_nonsys <= (others => '0');
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else
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iserror := or_reduce(syndrome) = '1';
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if iserror then
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if correction_en then
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-- Note: wrong_bit refers to the wrong bit of the code in
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-- non-systematic form. Indeed this is swapped to
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-- systematic form for the output.
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log_wrong_bit_pos_data_o_nonsys(wrong_bit-1) <= '1';
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end if;
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end if;
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end if;
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end if;
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end process log_wrong_bit_proc;
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end generate log_wrong_bit_gen;
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end architecture std;
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