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-------------------------------------------------------------------------------
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-- Yahamm IP core
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--
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-- This file is part of the Yahamm project
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-- http://www.opencores.org/cores/yahamm
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--
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-- Description
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-- A hamming encoder and decoder with single-error correcting and
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-- double-error detecting capability. The message length can be configured
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-- through a generic. Both the code generator matrix and the parity-check
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-- matrix are computed in the VHDL itself.
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--
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-- To Do:
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-- - write docs
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--
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-- Author:
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-- - Nicola De Simone, ndesimone@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2017 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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--- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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-- CORRECT: set to true to correct errors at the cost of decreasing error
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-- detection (see table).
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--
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-- SEC = single bit error corrected
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-- SED = single bit error detected
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-- DED = double bit error detected
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-- TED = triple bit error detected
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--
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-- EXTRA_PARITY_BIT | CORRECT FALSE TRUE
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-------------------------------------------------------------------------------
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-- FALSE | SED-DED SEC
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-- -----------------------------------------------------------
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-- TRUE | SED-DED-TED SEC-DED
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-------------------------------------------------------------------------------
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--
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-- Note that, for example, SEC-DED (EXTRA_PARITY_BIT = true, CORRECT =
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-- true) means that triple bit errors are not detected and messages
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-- will be wrongly corrected because the correction corrects toward
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-- the code word within the smaller hamming distance. Practically you
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-- usually know that something is very wrong with your communication
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-- channel because you will also see double bit errors. Then you
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-- should not trust corrected data at all.
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library ieee;
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use ieee.std_logic_1164.all;
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library yahamm;
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use yahamm.matrix_pkg.all;
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use yahamm.yahamm_pkg.all;
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entity yahamm_enc is
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generic (
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MESSAGE_LENGTH : natural := 5;
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EXTRA_PARITY_BIT : natural range 0 to 1 := 1;
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ONE_PARITY_BIT : boolean := false
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);
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port(
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clk_i, rst_i : in std_logic;
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en_i : in std_logic := '1'; -- Synchronous output enable .
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data_i : in std_logic_vector(MESSAGE_LENGTH - 1 downto 0); -- Input data.
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data_o : out std_logic_vector(MESSAGE_LENGTH - 1 downto 0); -- Out data.
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data_valid_o : out std_logic;
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parity_o : out std_logic_vector(calc_nparity_bits(MESSAGE_LENGTH, ONE_PARITY_BIT) + EXTRA_PARITY_BIT - 1 downto 0) -- Parity bits.
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);
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end yahamm_enc;
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architecture std of yahamm_enc is
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constant NPARITY_BITS : natural := calc_nparity_bits(MESSAGE_LENGTH, ONE_PARITY_BIT);
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constant BLOCK_LENGTH : natural := calc_block_length(MESSAGE_LENGTH, ONE_PARITY_BIT);
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constant G : matrix_t(0 to BLOCK_LENGTH + EXTRA_PARITY_BIT - 1,
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0 to BLOCK_LENGTH - NPARITY_BITS - 1) :=
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get_code_generator_matrix(MESSAGE_LENGTH, EXTRA_PARITY_BIT, ONE_PARITY_BIT);
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-- G'reverse_range(1) doesn't work in ghdl 0.34
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--signal code_sys : std_ulogic_vector(G'reverse_range(1)); -- systematic code
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signal code_sys : std_ulogic_vector(BLOCK_LENGTH + EXTRA_PARITY_BIT -1 downto 0); -- systematic code
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signal data_i_padded : bit_vector(BLOCK_LENGTH - NPARITY_BITS - 1 downto 0);
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begin
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check_parameters(BLOCK_LENGTH, NPARITY_BITS, MESSAGE_LENGTH, EXTRA_PARITY_BIT, ONE_PARITY_BIT);
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data_i_padded(MESSAGE_LENGTH - 1 downto 0) <= to_bitvector(data_i);
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pad_gen: if MESSAGE_LENGTH < BLOCK_LENGTH - NPARITY_BITS generate
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-- Pad data_i with zeros on the left, so that data_i_padded'length = BLOCK_LENGTH.
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-- This allow the user to reduce data_i width.
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data_i_padded(BLOCK_LENGTH - NPARITY_BITS - 1 downto MESSAGE_LENGTH) <= (others => '0');
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end generate pad_gen;
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-- Wire systematic code signal code_sys on data_o and parity_o output ports.
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-- Because of the form of the code generator matrix G, data are the LSB part
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-- of code and parity the MSB part.
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parity_o <= to_slv(code_sys(code_sys'high downto code_sys'high - (EXTRA_PARITY_BIT + NPARITY_BITS) + 1));
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data_o <= to_slv(code_sys(MESSAGE_LENGTH - 1 downto 0));
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-- purpose: Sequentially encode input with output enable.
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-- type : sequential
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-- inputs : clk_i, rst_i, d_sig
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-- outputs: msg_sys
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encode_proc: process (clk_i, rst_i) is
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begin -- process encode_proc
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if rst_i = '1' then -- asynchronous reset (active high)
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code_sys <= (others => '0');
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data_valid_o <= '0';
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elsif rising_edge(clk_i) then -- rising clock edge
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if en_i = '0' then -- syncronous output enable
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code_sys <= (others => '0');
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data_valid_o <= '0';
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else
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code_sys <= To_StdULogicVector(xor_multiply_vec(G, data_i_padded));
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data_valid_o <= '1';
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end if;
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end if;
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end process encode_proc;
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end architecture std;
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