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https://opencores.org/ocsvn/yahamm/yahamm/trunk
[/] [yahamm/] [trunk/] [rtl/] [vhdl/] [yahamm_enc.vhd] - Diff between revs 5 and 8
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-- A hamming encoder and decoder with single-error correcting and
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-- A hamming encoder and decoder with single-error correcting and
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-- double-error detecting capability. The message length can be configured
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-- double-error detecting capability. The message length can be configured
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-- through a generic. Both the code generator matrix and the parity-check
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-- through a generic. Both the code generator matrix and the parity-check
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-- matrix are computed in the VHDL itself.
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-- matrix are computed in the VHDL itself.
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--
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--
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-- To Do:
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-- - write docs
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--
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-- Author:
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-- Author:
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-- - Nicola De Simone, ndesimone@opencores.org
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-- - Nicola De Simone, ndesimone@opencores.org
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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port(
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port(
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clk_i, rst_i : in std_logic;
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clk_i, rst_i : in std_logic;
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en_i : in std_logic := '1'; -- Synchronous output enable .
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en_i : in std_logic := '1'; -- Synchronous output enable .
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data_i : in std_logic_vector(MESSAGE_LENGTH - 1 downto 0); -- Input data.
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data_i : in std_logic_vector(MESSAGE_LENGTH - 1 downto 0); -- Input data.
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data_o : out std_logic_vector(MESSAGE_LENGTH - 1 downto 0); -- Out data.
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data_o : out std_logic_vector(MESSAGE_LENGTH - 1 downto 0); -- Out data.
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data_valid_o : out std_logic;
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data_valid_o : out std_logic; -- High when data_o is valid.
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parity_o : out std_logic_vector(calc_nparity_bits(MESSAGE_LENGTH, ONE_PARITY_BIT) + EXTRA_PARITY_BIT - 1 downto 0) -- Parity bits.
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parity_o : out std_logic_vector(calc_nparity_bits(MESSAGE_LENGTH, ONE_PARITY_BIT) + EXTRA_PARITY_BIT - 1 downto 0) -- Parity bits.
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);
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);
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end yahamm_enc;
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end yahamm_enc;
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